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Observer chienpingwong
Registered: ‎06-30-2011

Timing of AXI interface MCB(MIG) ?

I am working on implement AXI interface MCB(MIG) to control DDR3. The timing of signal AWREADY from AXI document, is different from what I capture in chipscope. I am wondering, is this difference matter ? Will it lead to a writing error ?


Difference 1 :


in both pictures, red box is the signal AWREADY.

In ARM's document, this signal goes up then down, while AWVALID is high.

in my system, AWREADY signal goes down all the way until writing the last data do DDR3.



Difference 2 :


blue box are signals WVALID and WREADY

In ARM's document, these two signals goes up and down when burst write data to DDR

In my system, two signals keep high until writing the last data





http://mazsola.iit.uni-miskolc.hu/~drdani/docs_arm/AMBAaxi.pdf, page 1-9,

burst write.png



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