07-03-2018 06:26 AM
I have a DMA block on the PL side. I would like to use it to access and transfer data from the PL to PS, or to transfer data from PS-OCM to PS-DRAM. I have inserted a slave HPC port on the zynq and connected it to the AXI SMC. A screenshot of the design is attached.
The DMA works when I access the PL-side (BRAM or PL-DRAM), but it does not work when I access the PS-side. I get a DMA decode error whenever I access the DRAM or OCM memories. The address mapping of the design is also attached. I am running Linux on the PS.
Am I missing something in the design?
07-04-2018 05:17 AM
I did something similar to check the DDR4 SDRAM performance like in https://forums.xilinx.com/t5/Embedded-Boot-and-Configuration/ZYNQMP-configuration-for-access-PS-DDR-from-PL/m-p/831752#M231
Question to you: Are you aware that the PS is using AXI V3 and in PL we commonly use AXI V4?
07-04-2018 05:52 AM
Thanks for pointing out your topic. It seems related, but I did not catch the error.
Are the differences between AXI V3 and V4 not handled by the AXI smart connect? Should I change it to another block?
07-04-2018 06:07 AM
The point is that AXI V3 burst are 16 beats long and AXI V4 up to 256 beats long... Hence, to see if this is your problem try to restrict your DMA engine to 16 beats and see what happens.
07-04-2018 06:13 AM
The current configuration in the DMA block is max burst size of 8 for the reading channel and 16 for the writing channel. So it should not be the problem I believe.
Address width is 64 bits, memory map data width and stream data width are also 64 bits. Unaligned transfers is enabled, but micro DMA and scatter gather are disabled.
07-04-2018 06:19 AM - edited 07-04-2018 06:23 AM
The next step would be to see how the AXI communication proceeds. Can you add an ILA AXI bus analyzer to the connection to PS and have a look what you see? Is the address acknowledged and does the data stream as you configured/expect?
07-04-2018 07:27 AM
Ok, I will try that.
In the meantime, I changed the slave port on Zynq from HPC to ACP and got a different error. Instead of the DMA decode error, this time I got a DMASlveErr:
DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.
Which means that the addresses to access the PS-side memories are correct. However, why DMA may issue a slave error?
07-13-2018 06:06 AM
I changed the HPC port to HP and it partially worked. It was able to transfer data from PS DRAM to PL side and vice-versa. However, when PS-side OCM is involved, there is either a freezing on Linux or wrong values are transferred:
PS DRAM to OCM - freezes
PL DRAM to OCM - freezes
BRAM to OCM - freezes
OCM to BRAM - did not freeze but it has copied wrong values
OCM to PL DRAM - did not freeze but it has copied wrong values
OCM to PS DRAM - did not freeze but it has copied wrong values
07-20-2018 02:26 PM - edited 07-24-2018 12:51 PM
07-26-2018 02:21 PM
The AXI ILA is my preferred tool for such problems plus for checking the efficiency of transfers. Simply do it and you will see a lot more.