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Contributor
Contributor
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Registered: ‎09-02-2013

ULPI MIO Mapping in ZYNQ US+ MPSoC

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I am searching all over in the ZYNQ US+ TRM (UG1085).  I know it must be there.  I am blind and can't seem to find it.  I am looking for the MIO mapping for the USB0 core to the ULPI PHY.  Where is that located?  All of the other cores specify this.  I can't seem to find it.  If it is in another document, can someone point that out?  Thanks!

Bill

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Contributor
Contributor
132 Views
Registered: ‎09-02-2013

Re: ULPI MIO Mapping in ZYNQ US+ MPSoC

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I never found it in the TRM.  I am using the Vivado PS mapping.  I think this is a big hole Xilinx has left on their documentation.  In my review I would rather cite a document with the mapping rather than a software tool. 

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Contributor
Contributor
133 Views
Registered: ‎09-02-2013

Re: ULPI MIO Mapping in ZYNQ US+ MPSoC

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I never found it in the TRM.  I am using the Vivado PS mapping.  I think this is a big hole Xilinx has left on their documentation.  In my review I would rather cite a document with the mapping rather than a software tool. 

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