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Voyager
Voyager
553 Views
Registered: ‎05-30-2018

Using of the AXI Quad SPI v3.2 LogiCORE IP

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Hello,

In the Vivado example, generated for the AXI Quad SPI v3.2 (configured as Master) there is no ouput clock (sck_o port).

Is it normal ?

Thanks.

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1 Solution

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Xilinx Employee
Xilinx Employee
493 Views
Registered: ‎10-30-2017

Re: Using of the AXI Quad SPI v3.2 LogiCORE IP

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Hi @pavel_47,

 

It is expected behavior only. when ever the startup primitive enabled in the core then the sck signal is part of the core and not visible as output port. below is the figure when startup primitive is enabled.

no_sck.PNG

 

If I disable the Startup primitive like below

startup_primitive.PNG

 

then it will shows the sck signal as below:

with_sck.PNG

 

Please refer axi quad spi for more details.

 

Best Regards,
Srikanth
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2 Replies
Xilinx Employee
Xilinx Employee
494 Views
Registered: ‎10-30-2017

Re: Using of the AXI Quad SPI v3.2 LogiCORE IP

Jump to solution

Hi @pavel_47,

 

It is expected behavior only. when ever the startup primitive enabled in the core then the sck signal is part of the core and not visible as output port. below is the figure when startup primitive is enabled.

no_sck.PNG

 

If I disable the Startup primitive like below

startup_primitive.PNG

 

then it will shows the sck signal as below:

with_sck.PNG

 

Please refer axi quad spi for more details.

 

Best Regards,
Srikanth
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.

Voyager
Voyager
473 Views
Registered: ‎05-30-2018

Re: Using of the AXI Quad SPI v3.2 LogiCORE IP

Jump to solution

Great !

Thanks

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