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Observer jiv4ik
Observer
285 Views
Registered: ‎06-23-2017

Vivado 2018.3, Failed to synthesized ILA

Hi all,

I use Vivado 2018.3, on a Zybo board.

I create simple test design with AXI DMA loopback, with ILA.

axidma.png

When I try to synthesize a design, i see errors.

File ila_impl.xdc exists on disk.

source axidma_system_ila_0_0.tcl -notrace
WARNING: [Vivado 12-818] No files matched '/home/anton/Xilinx/axidma/axidma.srcs/sources_1/bd/axidma/ip/axidma_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila_impl.xdc'
ERROR: [Common 17-55] 'set_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
INFO: [Common 17-206] Exiting Vivado at Tue Feb 19 10:04:18 2019...

How to kill this error?

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3 Replies
Xilinx Employee
Xilinx Employee
249 Views
Registered: ‎01-09-2019

Re: Vivado 2018.3, Failed to synthesized ILA

Hello @jiv4ik 

How did you add the ILA?  Could you try removing the ILA, and then mark the lines you want debugged as 'Mark Debug'?  Then the Connection Automation banner should appear and that can add the ILA with all the necessary components.

What is the purpose of the .tcl script?  Could you synthesize without specifically sourcing that .tcl script?

The error seems to say it can't find that particular .xdc file and so is failing a get_property command.  That should be fixed by getting that file in the right spot with the right data.

Thanks,
Caleb
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Observer jiv4ik
Observer
232 Views
Registered: ‎06-23-2017

Re: Vivado 2018.3, Failed to synthesized ILA


Hello, @calebd !

Thanks for the answer!

How did you add the ILA?  Could you try removing the ILA, and then mark the lines you want debugged as 'Mark Debug'?  Then the Connection Automation banner should appear and that can add the ILA with all the necessary components.


I did everything that way. Mark the lines as 'Mark Debug'. Then Run Connection Automation. Then Run Synthesis.

What is the purpose of the .tcl script?  Could you synthesize without specifically sourcing that .tcl script?


This is an automatically generated script. I completely created my project through the design block. I did not add any of my sources to the project.

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Xilinx Employee
Xilinx Employee
218 Views
Registered: ‎01-09-2019

Re: Vivado 2018.3, Failed to synthesized ILA

Can you double check that the file exists in the location that it says in the error?

If that file is there, then it seems like that .tcl script isn't seeing the file for some reason.  Have you changed any of the file/folder structure created by Vivado?

Lastly, if you would be willing to try starting from scratch, that may fix your issue if something got stuck in Vivado making it not see properly where files are.  The example designs might speed up getting your design built (they don't seem to have your issue in them): https://www.xilinx.com/support/answers/57550.html

Thanks,
Caleb
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