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Contributor
Contributor
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Registered: ‎11-13-2018

Vivado Replacement for PLBv46 to DCR Bridge

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Hi,

I am working with Vivado 2018.2.

We are trying to port a project from ISE into Vivado. We were previously using a Virtex-5 and are upgrading to the Artix-7. Currently I am trying to create a block design using IP Integrator that mimics the functionality that was in the ISE project. Our project includes a MicroBlaze system.

The issue that I'm having is that we were using the PLBV46 to DCR Bridge core to read and write the registers in a shared register file. Obviously, this core is no longer available in Vivado due to the change to AXI. We are looking for a replacement for the PLBV46 to DCR Bridge core that has the same functionality, allowing us to read/write registers in a shared register file. 

Here's what I have found and attempted so far: 
1) I found the AXI4-Lite IPIF v3.0 Product Guide (PG155). This would be useful but it appears that it is no longer supported by Vivado because it does not appear in the IP Catalog.

2) I attempted to Create and Package New IP using UG1118 for reference. I am still working on this, but I am confused as to how I can make the master buses function as they did in DCR. The Package IP -> Ports and Interfaces window does not allow you to add custom (non-AXI) buses. I have read that you can add ports by editing the generated VHDL files. How is this usually done? How can I verify that the functionality is correct?


Ideally, we would not need to change our VHDL files in the actual project, except for changing signal names or mapping. I have only been working with Vivado for a month so I appreciate your patience and support. Any help you can provide would be useful. If anything I have mentioned here needs clarification, please let me know.

 

Thanks,
Brad

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Xilinx Employee
Xilinx Employee
356 Views
Registered: ‎02-01-2008

Re: Vivado Replacement for PLBv46 to DCR Bridge

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DCR is a relatively simple interface. The IPIF does exist but it is now considered a helper core that can be instantiated within your own source.

There are a few options available.

  1. If using Microblaze, take a look at the IOModule block. It has an IO_BUS that can be enabled and looks close to DCR. This IOModule uses LMB instead of AXI.
  2. Take a look at the AXI AHBLite Bridge. It may be close to the DCR signaling
  3. Create your own core that instantiates the IPIF (not my favorite choice)
  4. In Vivado, tools->create_and_package_IP, and create a new IP. There is a wizard that will walk you through creating a core that contains axiLite slave and even axiLite master. This wizard will create the hdl that interacts with the axiLite signalling so that you have full control instead of relying on an IPIF.

I hope you are using DocNav (Xilinx Documentation Navigator). In the 'design hub view' tab, you should be able to find documents that describe the IP packaging flow. Also, you should be able to find documentation that allows you to add custom buses and interfaces to IPI (if you want to add DCR to IPI).

 

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Xilinx Employee
Xilinx Employee
357 Views
Registered: ‎02-01-2008

Re: Vivado Replacement for PLBv46 to DCR Bridge

Jump to solution

DCR is a relatively simple interface. The IPIF does exist but it is now considered a helper core that can be instantiated within your own source.

There are a few options available.

  1. If using Microblaze, take a look at the IOModule block. It has an IO_BUS that can be enabled and looks close to DCR. This IOModule uses LMB instead of AXI.
  2. Take a look at the AXI AHBLite Bridge. It may be close to the DCR signaling
  3. Create your own core that instantiates the IPIF (not my favorite choice)
  4. In Vivado, tools->create_and_package_IP, and create a new IP. There is a wizard that will walk you through creating a core that contains axiLite slave and even axiLite master. This wizard will create the hdl that interacts with the axiLite signalling so that you have full control instead of relying on an IPIF.

I hope you are using DocNav (Xilinx Documentation Navigator). In the 'design hub view' tab, you should be able to find documents that describe the IP packaging flow. Also, you should be able to find documentation that allows you to add custom buses and interfaces to IPI (if you want to add DCR to IPI).

 

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Contributor
Contributor
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Registered: ‎11-13-2018

Re: Vivado Replacement for PLBv46 to DCR Bridge

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It looks like we will be able to use the IO Module Block with the IO Bus as long as the ready/acknowledge bits function similarly. If not I think we will be able to make it work. 

Thanks for your help!

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