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591 Views
Registered: ‎03-03-2017

Vivado/SDK 2018.3 download.bit not running Microblaze

I have a Kintex-7 325T project that worked just fine in Vivado/SDK 2018.1 but when I reimplemented in 2018.3 and rebuilt the application and tried to program the FPGA with the application.elf built into the download.bit Microblaze never starts and I never get any printf outputs out of the UART terminal output.   But, if I program the FPGA into bootloop and the manually run the application using Application->Run-As->Launch on Hardware (System Debugger) then it seems to work find.

How can I get the application to run out of download.bit?   Is there some new setting in Vivado/SDK 2018.3 that I may be missing?

Thanks.

Tim

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11 Replies
Observer luminal101
Observer
558 Views
Registered: ‎02-10-2017

Re: Vivado/SDK 2018.3 download.bit not running Microblaze

I'm having the same issue since upgrading to 2018.3. The S/W works fine when launching via the system debugger. But when using 'Program FPGA' (and choosing the generated .elf file for the software configuration) then the Microblaze doesn't seem to start.

I was using Vivado/SDK 2018.2.2 before without this issue. So I repeat Tim's question: What changed in 2018.3 that we seem to miss?

539 Views
Registered: ‎03-03-2017

Re: Vivado/SDK 2018.3 download.bit not running Microblaze

Fortunately I do not necessarily need to use 2018.3 so I am reverting back to 2018.1 until there is a solution to this problem.

Tim

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Visitor toulgaridis
Visitor
520 Views
Registered: ‎12-04-2015

Re: Vivado/SDK 2018.3 download.bit not running Microblaze

 

I shared a post yesterday reporting the same issue: link

It seems like there is a bug in .mmi file generation, but I am not sure yet.

If you find any solution please let me know.

Newbie ghhunter
Newbie
488 Views
Registered: ‎06-10-2017

Re: Vivado/SDK 2018.3 download.bit not running Microblaze

Unfortunately, I am facing the same problem. And I have always suspected that some settings are not properly configured.

Visitor toulgaridis
Visitor
453 Views
Registered: ‎12-04-2015

Re: Vivado/SDK 2018.3 download.bit not running Microblaze

We have found a solution, but it is sub-optimal. You have to edit the generated .mmi file:

I assume that you see the following pattern in the .mmi file (ignore the "<AddressSpace Name= ... "), using 32-bit BRAM Interface:

<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2018.3 (64-bit)              -->
<!-- SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018  -->
<!--                                                         -->
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.   -->
<!-- Dec  7 2018                                             -->
<!--                                                         -->
<!-- This file is generated by the software with the Tcl write_mem_info command. -->
<!-- Do not edit this file.                                                      -->

<MemInfo Version="1" Minor="6">
  <Processor Endianness="Little" InstPath="bd_i/SOFT_MB_SUB_SYS/SOFT_MB">
    <AddressSpace Name="bd_i_SOFT_MB_SUB_SYS_SOFT_MB.bd_i_SOFT_MB_SUB_SYS_SOFT_MB_LOCAL_MEMORY_dlmb_bram_if_cntlr" Begin="0" End="131071">
      <BusBlock>
        <BitLane MemType="RAMB36" Placement="X14Y24">
          <DataWidth MSB="0" LSB="0"/>
          <AddressRange Begin="0" End="32767"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
        <BitLane MemType="RAMB36" Placement="X17Y22">
          <DataWidth MSB="1" LSB="1"/>
          <AddressRange Begin="0" End="32767"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
        <BitLane MemType="RAMB36" Placement="X16Y26">
          <DataWidth MSB="2" LSB="2"/>
          <AddressRange Begin="0" End="32767"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>

.....

        <BitLane MemType="RAMB36" Placement="X15Y18">
          <DataWidth MSB="6" LSB="6"/>
          <AddressRange Begin="0" End="32767"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
        <BitLane MemType="RAMB36" Placement="X16Y23">
          <DataWidth MSB="7" LSB="7"/>
          <AddressRange Begin="0" End="32767"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>

.....

        <BitLane MemType="RAMB36" Placement="X14Y22">
          <DataWidth MSB="29" LSB="29"/>
          <AddressRange Begin="0" End="32767"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
        <BitLane MemType="RAMB36" Placement="X15Y19">
          <DataWidth MSB="30" LSB="30"/>
          <AddressRange Begin="0" End="32767"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
        <BitLane MemType="RAMB36" Placement="X15Y22">
          <DataWidth MSB="31" LSB="31"/>
          <AddressRange Begin="0" End="32767"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
      </BusBlock>
    </AddressSpace>

 I am referring to the Microblaze Local BRAM ONLY. In this configuration the BitLanes have the following order: 0, 1, 2, ... , 29, 30, 31.

The aforementioned order seems to cause the swapping problem I described in this thread.

So, you have to manually cut and paste the <BitLanes> in order to achieve the following order: 7, 6, ... , 2, 1, 0, 15, 14, ... , 9, 8, 23, 22, ... , 17, 16, 31, 30, ... , 25, 24.

It is important to maintain the "Placement=..." of a specific BitLane with the bit it corresponds to!

An example of an edited .mmi file would look something like this:

<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2018.3 (64-bit)              -->
<!-- SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018  -->
<!--                                                         -->
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.   -->
<!-- Dec  7 2018                                             -->
<!--                                                         -->
<!-- This file is generated by the software with the Tcl write_mem_info command. -->
<!-- Do not edit this file.                                                      -->

<MemInfo Version="1" Minor="6">
  <Processor Endianness="Little" InstPath="bd_i/SOFT_MB_SUB_SYS/SOFT_MB">
    <AddressSpace Name="bd_i_SOFT_MB_SUB_SYS_SOFT_MB.bd_i_SOFT_MB_SUB_SYS_SOFT_MB_LOCAL_MEMORY_dlmb_bram_if_cntlr" Begin="0" End="131071">
      <BusBlock>
        <BitLane MemType="RAMB36" Placement="X16Y23">
          <DataWidth MSB="7" LSB="7"/>
          <AddressRange Begin="0" End="32767"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
        <BitLane MemType="RAMB36" Placement="X15Y18">
          <DataWidth MSB="6" LSB="6"/>
          <AddressRange Begin="0" End="32767"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>

.....

        <BitLane MemType="RAMB36" Placement="X17Y22">
          <DataWidth MSB="1" LSB="1"/>
          <AddressRange Begin="0" End="32767"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
        <BitLane MemType="RAMB36" Placement="X14Y24">
          <DataWidth MSB="0" LSB="0"/>
          <AddressRange Begin="0" End="32767"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>

.....

    </AddressSpace>

 

For more information you can read this wiki.

Observer luminal101
Observer
396 Views
Registered: ‎02-10-2017

Re: Vivado/SDK 2018.3 download.bit not running Microblaze

I can confirm that this solution works. Thank you very much for sharing!

But then why is the .mmi file messed up in the first place? Is this simply a bug?

 

384 Views
Registered: ‎03-03-2017

Re: Vivado/SDK 2018.3 download.bit not running Microblaze

Xilinx, any response??

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Newbie ghhunter
Newbie
368 Views
Registered: ‎06-10-2017

Re: Vivado/SDK 2018.3 download.bit not running Microblaze

Thank you!  I have verified that this modification works. It would be nice to be able to modify the code that generates the .mmi file. This can reduce the probability of errors when manually modifying large .mmi files. At the same time, it can save time. It took more than 10 minutes to modify the 512kb .mmi file this afternoon. I hope that Xilinx can update the patch to fix this problem.

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353 Views
Registered: ‎03-03-2017

Re: Vivado/SDK 2018.3 download.bit not running Microblaze

Is it just me, or does it seem like Xilinx is responding less and less to these forums?   It seems like a year ago I was always getting responses within a day, but now I almost never get a response from Xilinx.

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Adventurer
Adventurer
123 Views
Registered: ‎05-04-2014

Re: Vivado/SDK 2018.3 download.bit not running Microblaze

I try this workaround and it works for me. Thank you very much. 

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Moderator
Moderator
111 Views
Registered: ‎09-12-2007

Re: Vivado/SDK 2018.3 download.bit not running Microblaze

This is a known issue, and a change request is filed to address this issue

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