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Observer novec_16
Observer
2,356 Views
Registered: ‎04-25-2017

What is the purpose of exposing CAN0 or CAN1 to MIO?

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I am wondering what is the purpose of exposing CAN0 or CAN1 to MIO.

Is this is an alternative to the option prescibed in the CAN 5.0 LogicCORE IP Product Guide which uses AXI CAN IP module?

It seems that the latter one takes care of generating interrupts and FIFO which may be very important to have.

But what if the system needs only simple messaging and polling is acceptable.

I was going to connect CAN PHY directly to the configured rx, tx MIO pins but not sure that it would be just a waste of time.

Thanks

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Observer novec_16
Observer
4,272 Views
Registered: ‎04-25-2017

Re: What is the purpose of exposing CAN0 or CAN1 to MIO?

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Herbert,

 

Thank you very much for your response.

I've asked this question because Xilinx is directing to the LogiCORE IP which is PL version of CAN implementation. It made me think that it is the way recommended for the production.

It is confusing for me that the Xilinx test application xcanps_polled_example.c works fine in loopback mode using PS only.

Also I did successfuly use Pmod RS232 connected to MIO and assumed using CAN the same way.

Some information about CAN controllers I've found in the UG585, however, I wish/need more details for programming.

I guess I need to try both implementation and find best suited for my application.

 

Best regards,

novec_16

 

 

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Voyager
Voyager
2,336 Views
Registered: ‎06-24-2013

Re: What is the purpose of exposing CAN0 or CAN1 to MIO?

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Hey @novec_16,

 

I am wondering what is the purpose of exposing CAN0 or CAN1 to MIO.

Most of the PS hardened peripherials can be configured to use MIO (PS MIO Pins via MIO Multiplexer) or EMIO (PL ports) which can then be routed to PL Pins.

 

Is this is an alternative to the option prescibed in the CAN 5.0 LogicCORE IP Product Guide which uses AXI CAN IP module?

Routing the PS I/O Peripherials (IOPs) to the PL can be seen as an alternative to instantiating a LogiCORE IP which provides similar functionality. Note that while the hardened PS Peripherials can be configure to some degree, they are not as flexible as logic.

 

It seems that the latter one takes care of generating interrupts and FIFO which may be very important to have.

The peripherials come equipped with their specific set of features, like FIFOs, etc and will usually work without PL interaction.

 

Hope this clarifies,

Herbert

-------------- Yes, I do this for fun!
Observer novec_16
Observer
4,273 Views
Registered: ‎04-25-2017

Re: What is the purpose of exposing CAN0 or CAN1 to MIO?

Jump to solution

Herbert,

 

Thank you very much for your response.

I've asked this question because Xilinx is directing to the LogiCORE IP which is PL version of CAN implementation. It made me think that it is the way recommended for the production.

It is confusing for me that the Xilinx test application xcanps_polled_example.c works fine in loopback mode using PS only.

Also I did successfuly use Pmod RS232 connected to MIO and assumed using CAN the same way.

Some information about CAN controllers I've found in the UG585, however, I wish/need more details for programming.

I guess I need to try both implementation and find best suited for my application.

 

Best regards,

novec_16

 

 

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Voyager
Voyager
2,285 Views
Registered: ‎06-24-2013

Re: What is the purpose of exposing CAN0 or CAN1 to MIO?

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@novec_16,

 

Thank you very much for your response.

You're welcome!

 

I guess I need to try both implementation and find best suited for my application.

Always a good approach, note that you can get some more details on the CAN peripherial from UG585 although the information is spread all over the place there.

 

Best,

Herbert

-------------- Yes, I do this for fun!
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