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Observer dougmiller
Observer
88 Views
Registered: ‎10-12-2017

Writes to Coresight registers via System APB have no effect

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I am using the APU in bare-metal mode and am trying to configure some Coresight registers. I can write them manually over JTAG, but writes from the APU seem to have no effect. For instance, I'm running the following code to modify the CTIGATE register for APU 0:

  volatile uint32_t * ptr_test = (volatile uint32_t *)0xFEC20140;
  uint32_t count = 1;
  while(1) {
    printf("\nDEBUG: iteration %u\n", count);
    printf("DEBUG: before: %p = 0x%08x\n", ptr_test, *ptr_test);
    printf("DEBUG: setting %p to 0...\n", ptr_test);
    *ptr_test = 0;
    printf("DEBUG: after: %p = 0x%08x\n", ptr_test, *ptr_test);
    for(int i = 0; i < (1 << 30); i++) {
      asm volatile("");
    }
    count++;
  }

Which outputs like

DEBUG: iteration 0
DEBUG: before: 0xfec20140 = 0x0000000e
DEBUG: setting 0xfec20140 to 0...
DEBUG: after: 0xfec20140 = 0x0000000e

DEBUG: iteration 1
DEBUG: before: 0xfec20140 = 0x0000000e
DEBUG: setting 0xfec20140 to 0...
DEBUG: after: 0xfec20140 = 0x0000000e

and so on. If I then go and manually adjust the value using mwr in xsct, then the APU does immediately see the change, but still cannot write

DEBUG: iteration 51
DEBUG: before: 0xfec20140 = 0x0000000c
DEBUG: setting 0xfec20140 to 0...
DEBUG: after: 0xfec20140 = 0x0000000c

I also have tried to read and write the value using the PL (S_AXI_LPD), which behaves similarly: reads return the correct value, writes appear to succeed (BRESP returns OKAY), but writes do not seem to actually modify the value. Note that this behavior also seems to happen for any write in the CoreSight address map (ug1085 figure 39-7). I do not have isolation enabled, the processor was running in EL3, and the PL was issuing secure (AxPROT = '0) transactions, and the fact that I'm reading correct values seems to imply there is not an authentication or permissions issue here. I found one part of ug1085 in Chapter 39 that seems to be relevant: 

paddr[31]=1 and paddr[31]=0 are subject to different authentications. This is useful for
preventing rogue software on the RPU or APU MPCore from interfering with CoreSight
components.
but there isn't any explanation of the different authentications. The jtag_dap_cfg register (0xFFCA003C) is the only authentication-based register I found in ug1087, and it's set to 0xFF (all modes enabled), so I'm not sure what else I need to do to be able to touch these registers.
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1 Solution

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Xilinx Employee
Xilinx Employee
53 Views
Registered: ‎09-01-2014

Re: Writes to Coresight registers via System APB have no effect

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you need to manually unlock it in your C code.
https://www.xilinx.com/html_docs/registers/ug1087/a53_cti_0___lar.html#
1 Reply
Xilinx Employee
Xilinx Employee
54 Views
Registered: ‎09-01-2014

Re: Writes to Coresight registers via System APB have no effect

Jump to solution
you need to manually unlock it in your C code.
https://www.xilinx.com/html_docs/registers/ug1087/a53_cti_0___lar.html#