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Observer matteo.geromin
Observer
4,350 Views
Registered: ‎12-20-2012

XADC VREF reads '0' after FPGA reconfiguration through XDEVCFG

Hello,

 

I'm working on a custom Zynq 7020 board,

I can correctly read all the XADC inputs from linux, even if I have the FPGA pre-programmed by FSBL or U-boot.

When I try to reconfigure the FPGA in Linux I read '0' value on VREF inputs:

 

root@zynq:~# cat /sys/bus/iio/devices/iio\:device0/in_voltage6_vrefp_raw
1704
root@zynq:~# cat /sys/bus/iio/devices/iio\:device0/in_voltage7_vrefn_raw
4095
root@zynq:~# cat bitstream.bin > /dev/xdevcfg

root@zynq:~# cat /sys/bus/iio/devices/iio\:device0/in_voltage6_vrefp_raw
0
root@zynq:~# cat /sys/bus/iio/devices/iio\:device0/in_voltage7_vrefn_raw
0

 

 

Even if it is the same bitstream programmed from FSBL or U-boot.

All the internal voltage and temperature values are ok, before and after the FPGA reconfiguration.

The FPGA project do not contains any XADC IP.

U-boot and Kernel are based on official Xilinx Repository (tag v2014.4)

There is a solution to this issue?

 

ThankYou in advance

 

Best Regards

Matteo Geromin

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1 Reply
Xilinx Employee
Xilinx Employee
4,268 Views
Registered: ‎03-21-2008

Re: XADC VREF reads '0' after FPGA reconfiguration through XDEVCFG

Hi Matteo,

 

The xadc registers are being reset to 0 by the bitstream load, which is normal. The reason vrefp and vrefn stay at zero is because the xadc configuration specified in the bitstream is not enabling these channels. To change this you can configure the xadc to convert on these channels via the bitstream, or after the load from the PS. 

 

Cheers,

John

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