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Visitor ashish7724
Visitor
208 Views
Registered: ‎04-21-2016

XSPI in Slave Mode for Spartan 6

Hello.

 I am willing to design a Master Slave communication between two FPGAs.

I have master SPI FPGA, which I have tested using loopback mode, it is working.

I have used another FPGA for slave module, whose SPISEL is connected to SS(0) of master. For both master and slave i have kept 10MHz SPI Clk.

 

I have changed control register for SPI Mode 0 in Slave configuration for slave FPGA.

 

I am stuck at Xspi_transfer

 

Here is my code

#define control_set_slave 0x082

void send_direct_spi_slave()
{
unsigned char spi_send_data[100],spi_recv_data[100];
unsigned char status,j,i;

spi_send_data[0] = 0xF4 ;
spi_send_data[1] = 0xFA ;
spi_send_data[2] = 0x00;
spi_send_data[3] = 0x12;

XSpi_Initialize(&Spi_S_Instance, XPAR_XPS_SPI_SLAVE_DEVICE_ID); //Initialise


XSpi_Start(&Spi_S_Instance); //Start SPI

// XSpi_SetControlReg(&Spi_S_Instance, control_set_slave); //Set Control


// XSpi_SetSlaveSelect(&Spi_S_Instance, 1);

XSpi_IntrGlobalDisable(&Spi_S_Instance); //Use SPI Polling

XSpi_Transfer(&Spi_S_Instance,spi_send_data,spi_recv_data,8);

// XSpi_SetSlaveSelect(&Spi_S_Instance, 0);

// XSpi_Stop(&Spi_S_Instance); //Stop SPI 


for(i=0;i<4;i++)
{
 XUartLite_SendByte(XPAR_UARTLITE_1_BASEADDR,spi_recv_data[i]);
}

}

 

 

I ahve used example code from SDK repository but still the same issue.

I have checked all three input SCK,MISO,CS till FPGA. It is showing correct.

 

Please suggest something on it.

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