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Observer sepher
Observer
6,800 Views
Registered: ‎02-05-2008

Xilinx IIC IP core on Zedboard - strange behavior with repeated start

Dear all,

 

I've stumbled upon a strange issue while trying to use the Xilinx IIC IP-core. I will only need the IIC interface to send some data to an external IC on startup, so I've decided I'll keep things simple and go for the basic, low level functions taken from the Xilinx-provided libraries. The module I am testing my code with is:

 

http://www.digilentinc.com/Products/Detail.cfm?Prod=PMOD-TMP2

 

Here is my simple code:

 

#include <stdio.h>
#include "platform.h"
#include "xiic_l.h"

#define TEMP_SENSOR_ONCHIP_ADDRESS  0x4B

int main()
{
    volatile int i;
    unsigned char DataPtr[2];
    unsigned char ReadAddr[1] = {0x0B};

    init_platform();

    while(1)
    {
    	for(i=0; i<500000000; i++);

    	XIic_Send(XPAR_IIC_0_BASEADDR, TEMP_SENSOR_ONCHIP_ADDRESS, ReadAddr, 1, XIIC_REPEATED_START);
    	XIic_Recv(XPAR_IIC_0_BASEADDR, TEMP_SENSOR_ONCHIP_ADDRESS, DataPtr, 1, XIIC_STOP);

    	printf("ID register %d \n\r", DataPtr[0]);


    }
    return 0;
}

 What I'm getting as an output is:

 

logic analyzer output

 

It looks like the clock signal just stops at some point in time for reasons that are unknown to me. I've confirmed, that both the receive and send functions work in standalone mode, that is when writing or reading a certan number of bytes from the chips' base address. This behavior occurs only whenever I try to use the repeated start. This is a rather serious problem for me, because such mode of operation is necessary for randomly accessing one or more of multiple on-chip registers for reading/writing by giving its address first.

 

Did anyone have similar problem? Any suggestions on resolving this issue? Thank you all in advance.

 

Regards,

M.

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8 Replies
Highlighted
Observer matschkeks
Observer
6,614 Views
Registered: ‎07-27-2012

Re: Xilinx IIC IP core on Zedboard - strange behavior with repeated start

I'm facing the same issue currently. My logic analyzer shows the exact same waveform.

Did you solve your problem?
An answer would be awesome as this is currently a real blocker for my project.
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Observer sepher
Observer
6,587 Views
Registered: ‎02-05-2008

Re: Xilinx IIC IP core on Zedboard - strange behavior with repeated start

I ended up writing a bit-bang implementation of IIC using AXI GPIO core.

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Teacher muzaffer
Teacher
6,578 Views
Registered: ‎03-31-2012

Re: Xilinx IIC IP core on Zedboard - strange behavior with repeated start

Try inserting some delay between accesses and see if that helps.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Observer matschkeks
Observer
5,323 Views
Registered: ‎07-27-2012

Re: Xilinx IIC IP core on Zedboard - strange behavior with repeated start

Same issue here for quite some time already.

Something is not right with this I2C core to be honest. I'm fighting with this thing for two months now.

 

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Xilinx Employee
Xilinx Employee
5,320 Views
Registered: ‎08-02-2007

Re: Xilinx IIC IP core on Zedboard - strange behavior with repeated start

Hi,

 

There is an errata item with Zynq PS IIC for repeated start. Refer to http://www.xilinx.com/support/answers/60695.html

 

--Hem

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Observer sepher
Observer
5,262 Views
Registered: ‎02-05-2008

Re: Xilinx IIC IP core on Zedboard - strange behavior with repeated start

Once again I need to implement some I2C comunication for one of my projects, and the code still doesn't work. Anyone figured it out? 

 

@htsvn - sorry, but your suggestion won't work for me, I use the AXI IIC core, not the one implemented as a part of Zynq PS.

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Observer matschkeks
Observer
5,254 Views
Registered: ‎07-27-2012

Re: Xilinx IIC IP core on Zedboard - strange behavior with repeated start

Yeah.

I think I have it working flawlessly now. I needed to increase the SDA and SCL inertial delay in the core configuration.

The values you specify there are AXI clock cycles for a filtering circuit of the inputs. It seems, that I had short glitches on one of my busses. Which led to spurious start or stop conditions on the bus.

 

I set both values to 5 which means that the voltage levels are debounced for a time of 50ns when the AXI clock is 100MHz. That's the maximum value according to the I2C fast mode spec (400kHz). I also tested it with higher values and it worked, but why violate the spec if it works with lower values? YMMV.

 

On one bus, I didn't need to do that. On another, it was totally unrealiable without filtering.

 

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Observer sepher
Observer
5,200 Views
Registered: ‎02-05-2008

Re: Xilinx IIC IP core on Zedboard - strange behavior with repeated start

Still not working for me. I guess I'll stick to my GPIO-based driver. I should have figured out there's a reason every reference design I see is not based on the Xilinx-provided drivers ;).

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