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Visitor mengnantiger
Visitor
11,578 Views
Registered: ‎07-20-2014

ZC702 's 2nd ethernet via emio without MDIO

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Hi All,

 

    I have a problem about the ethernet port with zynq , my project has 2 ethernet ports, one is from PS through mio , the other is connected to PL through EMIO .My OS is Linux.

 

    I want to transmit/receive eth packets from PL to PS directly ,so I do not need PHY. So I don't connected the eth1's port to the external pins of PL. I write a verilog module to transmit/receive eth packet , and I connect the emio port to this module.

 

    Now my linux can find two ethernet ports ,but when I start transmit eth packet, there is no response.

 

    I want to let the eth1 fix on 1000Mbps , but I don't konw how to remove the eth1's mdio interface and modify the devicetree.

 

    I remove some sentences about mdio in devicetree, then the linux hang up .

 

    I add "fixed-link = <1 1 1000 0 0>"; but there is no use.

 

    Below is some codes of my project , ignore my poor english.  thank u .

   

1, device tree which can boot the linux  

 

2, device tree which hang up the linux boot

 

3, linux log when hang up

 

4, my top vhdl code in PL

 

1, device tree which can boot the linux  

//============================================================================

ps7_ethernet_1: ps7-ethernet@e000c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "xlnx,ps7-ethernet-1.00.a";
interrupt-parent = <&ps7_scugic_0>;
interrupts = < 0 45 4 >;
local-mac-address = [ 00 0a 35 00 00 01 ];
phy-handle = <&phy1>;
reg = < 0xe000c000 0x1000 >;
xlnx,enet-clk-freq-hz = <0x7735940>;
xlnx,enet-reset = <0xffffffff>;
xlnx,enet-slcr-1000mbps-div0 = <0x1>;
xlnx,enet-slcr-1000mbps-div1 = <0x1>;
xlnx,enet-slcr-100mbps-div0 = <0x1>;
xlnx,enet-slcr-100mbps-div1 = <0x5>;
xlnx,enet-slcr-10mbps-div0 = <0x1>;
xlnx,enet-slcr-10mbps-div1 = <0x32>;
/*xlnx,eth-mode = <0x0>;*/
xlnx,has-mdio = <0x1>;
xlnx,ptp-enet-clock = <111111115>;
fixed-link = <1 1 1000 0 0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy1: phy@7 {
compatible = "marvell,88e1111";
device_type = "ethernet-phy";
reg = <7>;
} ;
} ;
} ;

//=================================================================================

 

 

2, device tree which hang up the linux boot , I remove the red words

//=================================================================================

ps7_ethernet_1: ps7-ethernet@e000c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "xlnx,ps7-ethernet-1.00.a";
interrupt-parent = <&ps7_scugic_0>;
interrupts = < 0 45 4 >;
local-mac-address = [ 00 0a 35 00 00 01 ];
/*phy-handle = <&phy1>;*/
reg = < 0xe000c000 0x1000 >;
xlnx,enet-clk-freq-hz = <0x7735940>;
xlnx,enet-reset = <0xffffffff>;
xlnx,enet-slcr-1000mbps-div0 = <0x1>;
xlnx,enet-slcr-1000mbps-div1 = <0x1>;
xlnx,enet-slcr-100mbps-div0 = <0x1>;
xlnx,enet-slcr-100mbps-div1 = <0x5>;
xlnx,enet-slcr-10mbps-div0 = <0x1>;
xlnx,enet-slcr-10mbps-div1 = <0x32>;
/*xlnx,eth-mode = <0x0>;*/
xlnx,has-mdio = <0x0>;
xlnx,ptp-enet-clock = <111111115>;
fixed-link = <1 1 1000 0 0>;
/*mdio {
#address-cells = <1>;
#size-cells = <0>;
phy1: phy@7 {
compatible = "marvell,88e1111";
device_type = "ethernet-phy";
reg = <7>;
} ;
} ;*/
} ;

//===========================================================================

 

3,linux log when hang

//===========================================================================

U-Boot 2012.10 (Jul 16 2014 - 15:34:15)
DRAM: 1 GiB
WARNING: Caches not enabled
MMC: SDHCI: 0
SF: Detected N25Q128A with page size 64 KiB, total 16 MiB
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: zynq_gem
Hit any key to stop autoboot: 0 
Copying Linux from SD to RAM...
Device: SDHCI
Manufacturer ID: 3
OEM: 5344
Name: SD08G 
Tran Speed: 25000000
Rd Block Len: 512
SD version 2.0
High Capacity: Yes
Capacity: 7.4 GiB
Bus Width: 4-bit
reading uImage
2881840 bytes read
reading devicetree.dtb
7872 bytes read
reading uramdisk.image.gz
5496224 bytes read
## Booting kernel from Legacy Image at 03000000 ...
Image Name: Linux-3.6.0-xilinx
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 2881776 Bytes = 2.7 MiB
Load Address: 00008000
Entry Point: 00008000
Verifying Checksum ... OK
## Loading init Ramdisk from Legacy Image at 02000000 ...
Image Name: 
Image Type: ARM Linux RAMDisk Image (gzip compressed)
Data Size: 5496160 Bytes = 5.2 MiB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
## Flattened Device Tree blob at 02a00000
Booting using the fdt blob at 0x02a00000
Loading Kernel Image ... OK
OK
Loading Ramdisk to 1fac2000, end 1ffffd60 ... OK
Loading Device Tree to 1fabd000, end 1fac1ebf ... OK
Starting kernel ...
Uncompressing Linux... done, booting the kernel.
Booting Linux on physical CPU 0
Linux version 3.6.0-xilinx (root@mengnan-virtual-machine) (gcc version 4.6.3 (Sourcery CodeBench Lite 2012.03-79) ) #4 SMP PREEMPT Wed Jul 16 14:47:18 CST 2014
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine: Xilinx Zynq Platform, model: Xilinx Zynq
bootconsole [earlycon0] enabled
cma: CMA: reserved 16 MiB at 2e800000
Memory policy: ECC disabled, Data cache writealloc
PERCPU: Embedded 7 pages/cpu @c0d89000 s7488 r8192 d12992 u32768
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 260096
Kernel command line: console=ttyPS0,115200 root=/dev/ram rw ip=192.168.1.10 earlyprintk
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 1024MB = 1024MB total
Memory: 1012032k/1012032k available, 36544k reserved, 270336K highmem
Virtual kernel memory layout:
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
vmalloc : 0xf0000000 - 0xff000000 ( 240 MB)
lowmem : 0xc0000000 - 0xef800000 ( 760 MB)
pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
.text : 0xc0008000 - 0xc04e5ccc (4984 kB)
.init : 0xc04e6000 - 0xc050cd40 ( 156 kB)
.data &colon; 0xc050e000 - 0xc0554800 ( 282 kB)
.bss : 0xc0554824 - 0xc057ea30 ( 169 kB)
Preemptible hierarchical RCU implementation.
Dump stacks of tasks blocking RCU-preempt GP.
RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
NR_IRQS:512
Zynq clock init
xlnx,ps7-ttc-1.00.a #0 at 0xf0000000, irq=43
sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps every 4294967286ms
Console: colour dummy device 80x30
Calibrating delay loop... 1332.01 BogoMIPS (lpj=6660096)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available
Setting up static identity map for 0x38bbc0 - 0x38bbf4
L310 cache controller enabled
l2x0: 8 ways, CACHE_ID 0x410000c8, AUX_CTRL 0x72360000, Cache size: 524288 B
Map SLCR registers
CPU1: Booted secondary processor
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
Brought up 2 CPUs
SMP: Total of 2 processors activated (2664.03 BogoMIPS).
devtmpfs: initialized
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
xgpiops e000a000.ps7-gpio: gpio at 0xe000a000 mapped to 0xf0008000
registering platform device 'pl330' id 0
registering platform device 'arm-pmu' id 0
registering platform device 'zynq-dvfs' id 0
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
MIO pin 47 not assigned(00001220)
xslcr xslcr.0: at 0xF8000000 mapped to 0xF8000000
bio: create slab <bio-0> at 0
vgaarb: loaded
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
Switching to clocksource xttcpss_timer1
NET: Registered protocol family 2
TCP established hash table entries: 131072 (order: 8, 1048576 bytes)
TCP bind hash table entries: 65536 (order: 7, 524288 bytes)
TCP: Hash tables configured (established 131072 bind 65536)
TCP: reno registered
UDP hash table entries: 512 (order: 2, 16384 bytes)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
Trying to unpack rootfs image as initramfs...
rootfs image is not initramfs (no cpio magic); looks like an initrd
Freeing initrd memory: 5364K
pl330 dev 0 probe success
bounce pool size: 64 pages
jffs2: version 2.2. (NAND) (SUMMARY) 漏 2001-2006 Red Hat, Inc.
msgmni has been set to 1491
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
e00010console [ttyPS0] enabled, bootconsole disabled
console [ttyPS0] enabled, bootconsole disabled
xdevcfg f8007000.ps7-dev-cfg: ioremap f8007000 to f005c000 with size 1000
brd: module loaded
loop: module loaded
xqspips e000d000.ps7-qspi: master is unqueued, this is deprecated
xqspips e000d000.ps7-qspi: at 0xE000D000 mapped to 0xF005E000, irq=51
e1000e: Intel(R) PRO/1000 Network Driver - 2.0.0-k
e1000e: Copyright(c) 1999 - 2012 Intel Corporation.
libphy: XEMACPS mii bus: probed
xemacps e000b000.ps7-ethernet: pdev->id -1, baseaddr 0xe000b000, irq 54
libphy: XEMACPS mii bus: probed
Unable to handle kernel NULL pointer dereference at virtual address 0000001c
pgd = c0004000
[0000001c] *pgd=00000000
Internal error: Oops: 5 [#1] PREEMPT SMP ARM
Modules linked in:
CPU: 0 Not tainted (3.6.0-xilinx #4)
PC is at of_get_next_child+0x1c/0x34
LR is at of_get_next_child+0x14/0x34
pc : [<c02d43a4>] lr : [<c02d439c>] psr: 60000113
sp : ee057e88 ip : ee056008 fp : 00000000
r10: ee2d6480 r9 : ee2dd000 r8 : 00000000
r7 : 00000000 r6 : 00000000 r5 : 00000000 r4 : 00000000
r3 : 00000000 r2 : 00000000 r1 : 00000000 r0 : c0579a04
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: 18c5387d Table: 0000404a DAC: 00000015
Process swapper/0 (pid: 1, stack limit = 0xee0562f0)
Stack: (0xee057e88 to 0xee058000)
7e80: 00000080 ee2dd000 ee08ee08 c02d8238 00000000 ee08ee00
7ea0: ee2dd000 ee2d6480 00000000 ee2d6000 ee08ee08 00000000 00000000 ee08ee00
7ec0: ee2d6480 c038059c c01f68d8 00000000 00000000 c00eaa58 ee08ee08 c01f68d8
7ee0: ee052c40 00000003 ee08dcc8 00000000 c053ddec ee08ee08 ee08ee08 c053ddec
7f00: c053ddec 00000000 c0509d7c 00000000 00000000 c01f3320 c01f330c c01f227c
7f20: c053ddec ee08ee08 ee08ee08 ee08ee3c c053ddec c01f24d8 c053ddec c01f2478
7f40: 00000000 c01f0a18 ee052c18 ee08cef4 c053ddec c05368c0 ee1bb0c0 c01f1888
7f60: c047c9ba 00000001 c053ddec c04fb900 00000000 00000089 c0509d7c c01f2808
7f80: 00000000 ee057fa0 c04fb900 00000000 00000089 c0509d7c 00000000 c00085ac
7fa0: 00000006 00000006 c052cc04 00000006 c050490c 00000006 c0504910 c05048f0
7fc0: 00000089 c0509d7c 00000000 c04e68d0 00000006 00000006 c04e61bc 00000000
7fe0: 00000000 c04e67d8 c000eb70 00000013 00000000 c000eb70 5ffffefe ee67fd4f
[<c02d43a4>] (of_get_next_child+0x1c/0x34) from [<c02d8238>] (of_mdiobus_register+0x1a8/0x1dc)
[<c02d8238>] (of_mdiobus_register+0x1a8/0x1dc) from [<c038059c>] (xemacps_probe+0x424/0x6e4)
[<c038059c>] (xemacps_probe+0x424/0x6e4) from [<c01f3320>] (platform_drv_probe+0x14/0x18)
[<c01f3320>] (platform_drv_probe+0x14/0x18) from [<c01f227c>] (driver_probe_device+0x130/0x32c)
[<c01f227c>] (driver_probe_device+0x130/0x32c) from [<c01f24d8>] (__driver_attach+0x60/0x84)
[<c01f24d8>] (__driver_attach+0x60/0x84) from [<c01f0a18>] (bus_for_each_dev+0x48/0x74)
[<c01f0a18>] (bus_for_each_dev+0x48/0x74) from [<c01f1888>] (bus_add_driver+0xbc/0x234)
[<c01f1888>] (bus_add_driver+0xbc/0x234) from [<c01f2808>] (driver_register+0x9c/0x138)
[<c01f2808>] (driver_register+0x9c/0x138) from [<c00085ac>] (do_one_initcall+0x90/0x160)
[<c00085ac>] (do_one_initcall+0x90/0x160) from [<c04e68d0>] (kernel_init+0xf8/0x1b8)
[<c04e68d0>] (kernel_init+0xf8/0x1b8) from [<c000eb70>] (kernel_thread_exit+0x0/0x8)
Code: e1a05001 eb02dc21 e3550000 e59f0010 (0594401c) 
---[ end trace 559f70820bd14609 ]---
note: swapper/0[1] exited with preempt_count 1

 

//===========================================================================

 

4. the top of my PL code.

 //===========================================================================

module system_stub
(
processing_system7_0_MIO,
processing_system7_0_PS_SRSTB,
processing_system7_0_PS_CLK,
processing_system7_0_PS_PORB,
processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB_pin,
processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP,
//---------------------------------------------
//processing_system7_0_ENET1_GMII_TX_EN_pin,
//processing_system7_0_ENET1_GMII_TX_ER_pin,
//processing_system7_0_ENET1_MDIO_MDC_pin,
//processing_system7_0_ENET1_PTP_DELAY_REQ_RX_pin,
//processing_system7_0_ENET1_PTP_DELAY_REQ_TX_pin,
//processing_system7_0_ENET1_PTP_PDELAY_REQ_RX_pin,
//processing_system7_0_ENET1_PTP_PDELAY_REQ_TX_pin,
//processing_system7_0_ENET1_PTP_PDELAY_RESP_RX_pin,
//processing_system7_0_ENET1_PTP_PDELAY_RESP_TX_pin,
//processing_system7_0_ENET1_PTP_SYNC_FRAME_RX_pin,
//processing_system7_0_ENET1_PTP_SYNC_FRAME_TX_pin,
//processing_system7_0_ENET1_SOF_RX_pin,
//processing_system7_0_ENET1_SOF_TX_pin,
//processing_system7_0_ENET1_GMII_TXD_pin,
//processing_system7_0_ENET1_GMII_COL_pin,
//processing_system7_0_ENET1_GMII_CRS_pin,
//processing_system7_0_ENET1_EXT_INTIN_pin,
//processing_system7_0_ENET1_GMII_RX_CLK_pin,
//processing_system7_0_ENET1_GMII_RX_DV_pin,
//processing_system7_0_ENET1_GMII_RX_ER_pin,
//processing_system7_0_ENET1_GMII_TX_CLK_pin,
//processing_system7_0_ENET1_GMII_RXD_pin,
//processing_system7_0_ENET1_MDIO_pin,
//----------------------------------------------
//O_config_0,
//O_config_1,
//O_config_2,
//O_config_3,
//O_config_4,
//O_config_5,
//O_config_6,
//I_config_7,
I_usr_clk_p,
I_usr_clk_n
);
inout [53:0] processing_system7_0_MIO;
input processing_system7_0_PS_SRSTB;
input processing_system7_0_PS_CLK;
input processing_system7_0_PS_PORB;
inout processing_system7_0_DDR_Clk;
inout processing_system7_0_DDR_Clk_n;
inout processing_system7_0_DDR_CKE;
inout processing_system7_0_DDR_CS_n;
inout processing_system7_0_DDR_RAS_n;
inout processing_system7_0_DDR_CAS_n;
output processing_system7_0_DDR_WEB_pin;
inout [2:0] processing_system7_0_DDR_BankAddr;
inout [14:0] processing_system7_0_DDR_Addr;
inout processing_system7_0_DDR_ODT;
inout processing_system7_0_DDR_DRSTB;
inout [31:0] processing_system7_0_DDR_DQ;
inout [3:0] processing_system7_0_DDR_DM;
inout [3:0] processing_system7_0_DDR_DQS;
inout [3:0] processing_system7_0_DDR_DQS_n;
inout processing_system7_0_DDR_VRN;
inout processing_system7_0_DDR_VRP;
//----------------------------------------------------------
//output processing_system7_0_ENET1_GMII_TX_EN_pin;
//output processing_system7_0_ENET1_GMII_TX_ER_pin;
//output processing_system7_0_ENET1_MDIO_MDC_pin;
//output processing_system7_0_ENET1_PTP_DELAY_REQ_RX_pin;
//output processing_system7_0_ENET1_PTP_DELAY_REQ_TX_pin;
//output processing_system7_0_ENET1_PTP_PDELAY_REQ_RX_pin;
//output processing_system7_0_ENET1_PTP_PDELAY_REQ_TX_pin;
//output processing_system7_0_ENET1_PTP_PDELAY_RESP_RX_pin;
//output processing_system7_0_ENET1_PTP_PDELAY_RESP_TX_pin;
//output processing_system7_0_ENET1_PTP_SYNC_FRAME_RX_pin;
//output processing_system7_0_ENET1_PTP_SYNC_FRAME_TX_pin;
//output processing_system7_0_ENET1_SOF_RX_pin;
//output processing_system7_0_ENET1_SOF_TX_pin;
//output [7:0] processing_system7_0_ENET1_GMII_TXD_pin;
//input processing_system7_0_ENET1_GMII_COL_pin;
//input processing_system7_0_ENET1_GMII_CRS_pin;
//input processing_system7_0_ENET1_EXT_INTIN_pin;
//input processing_system7_0_ENET1_GMII_RX_CLK_pin;
//input processing_system7_0_ENET1_GMII_RX_DV_pin;
//input processing_system7_0_ENET1_GMII_RX_ER_pin;
//input processing_system7_0_ENET1_GMII_TX_CLK_pin;
//input [7:0] processing_system7_0_ENET1_GMII_RXD_pin;
//inout processing_system7_0_ENET1_MDIO_pin;
//-----------------------------------------------------------
//output [31:0] O_config_0;
//output [31:0] O_config_1;
//output [31:0] O_config_2;
//output [31:0] O_config_3;
//output [31:0] O_config_4;
//output [31:0] O_config_5;
//output [31:0] O_config_6;
//input [31:0] I_config_7;
input I_usr_clk_n;
input I_usr_clk_p;


wire [31:0] S_config_0 ;
wire [31:0] S_config_1 ;
wire [31:0] S_config_2 ;
wire [31:0] S_config_3 ;
wire [31:0] S_config_4 ;
wire [31:0] S_config_5 ;
wire [31:0] S_config_6 ;
wire [31:0] S_config_7 ;
wire [7:0] S_pl2ps_eth_data ;
wire S_pl2ps_eth_data_dv ;
wire S_pl2ps_eth_clk ;
wire [7:0] S_ps2pl_eth_data ;
wire S_ps2pl_eth_data_dv ;
wire S_ps2pl_eth_clk ;

 

(* BOX_TYPE = "user_black_box" *)
system
system_i (
.processing_system7_0_MIO ( processing_system7_0_MIO ),
.processing_system7_0_PS_SRSTB ( processing_system7_0_PS_SRSTB ),
.processing_system7_0_PS_CLK ( processing_system7_0_PS_CLK ),
.processing_system7_0_PS_PORB ( processing_system7_0_PS_PORB ),
.processing_system7_0_DDR_Clk ( processing_system7_0_DDR_Clk ),
.processing_system7_0_DDR_Clk_n ( processing_system7_0_DDR_Clk_n ),
.processing_system7_0_DDR_CKE ( processing_system7_0_DDR_CKE ),
.processing_system7_0_DDR_CS_n ( processing_system7_0_DDR_CS_n ),
.processing_system7_0_DDR_RAS_n ( processing_system7_0_DDR_RAS_n ),
.processing_system7_0_DDR_CAS_n ( processing_system7_0_DDR_CAS_n ),
.processing_system7_0_DDR_WEB_pin ( processing_system7_0_DDR_WEB_pin ),
.processing_system7_0_DDR_BankAddr ( processing_system7_0_DDR_BankAddr ),
.processing_system7_0_DDR_Addr ( processing_system7_0_DDR_Addr ),
.processing_system7_0_DDR_ODT ( processing_system7_0_DDR_ODT ),
.processing_system7_0_DDR_DRSTB ( processing_system7_0_DDR_DRSTB ),
.processing_system7_0_DDR_DQ ( processing_system7_0_DDR_DQ ),
.processing_system7_0_DDR_DM ( processing_system7_0_DDR_DM ),
.processing_system7_0_DDR_DQS ( processing_system7_0_DDR_DQS ),
.processing_system7_0_DDR_DQS_n ( processing_system7_0_DDR_DQS_n ),
.processing_system7_0_DDR_VRN ( processing_system7_0_DDR_VRN ),
.processing_system7_0_DDR_VRP ( processing_system7_0_DDR_VRP ),
//--------------------------------------------------------------------------------------------
.processing_system7_0_ENET1_GMII_TX_EN_pin (S_ps2pl_eth_data_dv ),
.processing_system7_0_ENET1_GMII_TX_ER_pin ( ),
.processing_system7_0_ENET1_MDIO_MDC_pin ( ),
.processing_system7_0_ENET1_PTP_DELAY_REQ_RX_pin ( ),
.processing_system7_0_ENET1_PTP_DELAY_REQ_TX_pin ( ),
.processing_system7_0_ENET1_PTP_PDELAY_REQ_RX_pin ( ),
.processing_system7_0_ENET1_PTP_PDELAY_REQ_TX_pin ( ),
.processing_system7_0_ENET1_PTP_PDELAY_RESP_RX_pin ( ),
.processing_system7_0_ENET1_PTP_PDELAY_RESP_TX_pin ( ),
.processing_system7_0_ENET1_PTP_SYNC_FRAME_RX_pin ( ),
.processing_system7_0_ENET1_PTP_SYNC_FRAME_TX_pin ( ),
.processing_system7_0_ENET1_SOF_RX_pin ( ),
.processing_system7_0_ENET1_SOF_TX_pin ( ),
.processing_system7_0_ENET1_GMII_TXD_pin (S_ps2pl_eth_data ),
.processing_system7_0_ENET1_GMII_COL_pin (1'b0 ),
.processing_system7_0_ENET1_GMII_CRS_pin (1'b0 ),
.processing_system7_0_ENET1_EXT_INTIN_pin (1'b0 ),
.processing_system7_0_ENET1_GMII_RX_CLK_pin (S_pl2ps_eth_clk ),//input
.processing_system7_0_ENET1_GMII_RX_DV_pin (S_pl2ps_eth_data_dv ),
.processing_system7_0_ENET1_GMII_RX_ER_pin (1'b0 ),
.processing_system7_0_ENET1_GMII_TX_CLK_pin (S_pl2ps_eth_clk ),//input
.processing_system7_0_ENET1_GMII_RXD_pin (S_pl2ps_eth_data ),
.processing_system7_0_ENET1_MDIO_pin ( ),
//----------------------------------------------------------------------------------------
.O_config_0 ( S_config_0 ),
.O_config_1 ( S_config_1 ),
.O_config_2 ( S_config_2 ),
.O_config_3 ( S_config_3 ),
.O_config_4 ( S_config_4 ),
.O_config_5 ( S_config_5 ),
.O_config_6 ( S_config_6 ),
.I_config_7 ( S_config_7 )
);


usr_src
inst_usr_src
(
.I_usr_clk_p (I_usr_clk_p ),
.I_usr_clk_n (I_usr_clk_n ),
.I_config0 (S_config_0 ),//control
.I_config1 (S_config_1 ),//addr
.I_config2 (S_config_2 ),//data_wr
.I_config3 (S_config_3 ),
.I_config4 (S_config_4 ),
.I_config5 (S_config_5 ),
.I_config6 (S_config_6 ),
.O_config7 (S_config_7 ),//data_rd
.O_eth_data (S_pl2ps_eth_data ),
.O_eth_data_dv (S_pl2ps_eth_data_dv ),
.O_eth_clk (S_pl2ps_eth_clk ),
.I_eth_data (S_ps2pl_eth_data ),
.I_eth_data_dv (S_ps2pl_eth_data_dv )
);

endmodule

//=========================================================================================

    

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Accepted Solutions
Visitor mengnantiger
Visitor
10,636 Views
Registered: ‎07-20-2014

Re: ZC702 's 2nd ethernet via emio without MDIO

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Hi,

    I have solved it.

    I make the mdio to PL ,then I make some register in PL as mdio protocol to simulate as a phy, mdio interface itself is a group of address-based register . 

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4 Replies
Visitor mengnantiger
Visitor
11,577 Views
Registered: ‎07-20-2014

Re: ZC702 's 2nd ethernet via emio without MDIO

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In XPS, I find the selection of eth1's mdio is grey ,So is it possible to remove the mdio interface of eth1?

 

1.png

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Visitor cladtk81
Visitor
10,530 Views
Registered: ‎03-26-2015

Re: ZC702 's 2nd ethernet via emio without MDIO

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Hi, I have the same issue.

Did you solved it?

THanks

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Visitor mengnantiger
Visitor
10,637 Views
Registered: ‎07-20-2014

Re: ZC702 's 2nd ethernet via emio without MDIO

Jump to solution

Hi,

    I have solved it.

    I make the mdio to PL ,then I make some register in PL as mdio protocol to simulate as a phy, mdio interface itself is a group of address-based register . 

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Adventurer
Adventurer
239 Views
Registered: ‎08-04-2016

Re: ZC702 's 2nd ethernet via emio without MDIO

Jump to solution

Hi @mengnantiger 

If I understand correctly, you are "fooling" the PS that it is actually communicating with the PHY over MDIO. Is it possible for you to share your code that does this PHY MDIO emulation? I'm stuck with a similar problem.

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