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Visitor marius1234
Visitor
7,956 Views
Registered: ‎03-29-2014

ZYBO I2S BCLK

Hello!

 

I am trying to use the audio codec on the ZYBO board, but I am having a bit of hard time with the BCLK needed for the I2S protocol.

 

I have found and read datasheets and details about I2S, but there is this BCLK which I don't know what frequency it should have.

 

My application uses the standard 48kHz sampling rate and 24bit samples so the MCLK is at 12.288 MHz as suggested in the ZYBO manual.

 

Then there is this timing diagram:

 

Clipboard02.jpg

The explanation says that there is that N bit which is delayed when there is the shift from left to right channel. However, I didn't understand if that is just the LSB from the previous sample or an extra bit so I also checked the audio codec SSM2603 datasheet which had this diagram:

 

 

Clipboard01.jpg

Here I see that there are 2 extra bits, 1 before MSB and 1 after LSB. However, it is recommended that BCLK should be at least 2*sampling rate*nr of bits = 2* 48k * 24 in my case. But that doesn't take into account the 2 extra bits so it should be 2*sampling rate*( nr of bits + 2 ).

 

So this is where my problem is, which frequency does BCLK need 2*sampling rate*nr of bits or 2*sampling rate*( nr of bits + 2) or am I missing something?

 

The bad part is that I tried both and neither worked so I am not sure what else to try.

 

Thank you!

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7 Replies
Historian
Historian
7,945 Views
Registered: ‎02-25-2008

Re: ZYBO I2S BCLK

The frame is always 32 bits per sample, and there are two samples per frame, so you need 64 clocks to transfer a frame. So BCLK is always 64 times LRCLK. With 48 kHz sampling, BCLK is 3.072 MHz.

With 256x oversampling (modulator clock MCLK at Fs * 256), BCLK is MCLK / 4.

 

Note that you have to pad the samples. With I2S the assumption is that LRCLK and DOUT change on the falling edge of BCLK and are captured on the rising edge. The first bit time after a change in LRCLK is ignored, and then you shift bits out most significant first. Pad the remainder to the 32 bit boundary with zeros.

----------------------------Yes, I do this for a living.
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Visitor marius1234
Visitor
7,934 Views
Registered: ‎03-29-2014

Re: ZYBO I2S BCLK

Thanks for the reply!
Here is what my module does. I used what you said and made the sample 32 bits wide and the BCLK 3.072MHz. However this still doesn't work.

The clocks are provided by the PS PLL since I can tell XPS exactly which frequency to create even thought it won't give me the exact one but close enough I assume.

Another reason I thought might be the samples I used. I got them using a Python script to extract the values from a wav file. I used the same sample values in matlab to creata a wav and it worked so I assume the samples should create a sound.

Clipboard03.jpg

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Historian
Historian
7,928 Views
Registered: ‎02-25-2008

Re: ZYBO I2S BCLK


@marius1234 wrote:

Thanks for the reply!
Here is what my module does. I used what you said and made the sample 32 bits wide and the BCLK 3.072MHz. However this still doesn't work.


Define "doesn't work."

----------------------------Yes, I do this for a living.
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Visitor marius1234
Visitor
7,924 Views
Registered: ‎03-29-2014

Re: ZYBO I2S BCLK

By doesn't work I mean that there is no sound playing in the headphones. I don't know any other way of testing the audio codec. Maybe I will try to get my hands on an osciloscope to verify the signals I am sending.

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Historian
Historian
7,921 Views
Registered: ‎02-25-2008

Re: ZYBO I2S BCLK


@marius1234 wrote:

By doesn't work I mean that there is no sound playing in the headphones. I don't know any other way of testing the audio codec. Maybe I will try to get my hands on an osciloscope to verify the signals I am sending.


Yes, a 'scope is required.

I know nothing about this board, but perchance does the DAC require any sort of configuration? Some DACs have an SPI or I2C port which is used to set up internal registers; others have some pins which need to be pulled up or down to set the operating mode.

----------------------------Yes, I do this for a living.
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Visitor etb513
Visitor
7,868 Views
Registered: ‎03-17-2014

Re: ZYBO I2S BCLK

Hello,

 

I'm working with the ZYBO as well, and after having extensive issues getting any audio from the codec despite generating a correct master clock and I2S signals, I took some time to extensively read through the datasheet for the SSM2603 codec on the board.

 

This isn't mentioned in the ZYBO manual, but the codec actually needs to be manually powered on via its I2C ports. There is a sequence of steps you have to take:

 

1) Enable all needed power management bits in register R6 (except the out bit, which stays low until the end of the power-up sequence)

 

2) Program any other needed registers for misc configuration

 

3) Delay while the VMID decoupling capacitor charges

 

4) Enable the DAC by setting the out bit of R6 to 0.

 

Here is a link to the datasheet: http://www.analog.com/static/imported-files/data_sheets/SSM2603.pdf

 

I'm currently in the process of learning how to work with the PS so that I can use the I2C module in the PS, routed to the PL via EMIO and from there to the codec via IOBUF, to perform this startup sequence. I will let you know if I am able to get the codec functioning correctly this way. Likewise, let me know if you make any progress.

 

-Ethan

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Visitor gau_veldt
Visitor
1,878 Views
Registered: ‎10-22-2017

Re: ZYBO I2S BCLK

 

 


@etb513 wrote:

 

3) Delay while the VMID decoupling capacitor charges

 



This delay depends on the VMID cap's rating.

The SSM2603 docs provide a formula based on the rating: t = C × 25,000/3.5 

So does anyone know the rating of the VMID cap used on the Zybo board?

 

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