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Observer rgebauer
Registered: ‎07-17-2017

ZYNQ MPSoC - Fast AXI4-Lite Register read from R5

Hi everyone,

we are currently using AXI4-Lite interfaces connected to the ZYNQ PS via M_AXI_HPM0_FPD in order to read out and write registers in our hardware modules from both A53 and R5.

According to the top level block diagram of the MPSoC (p.23 of UG1182 for ZCU102), this happens for the R5 via quite some clock domain crossings (PL HPM - Central Switch - SMMU/CCI - Low Power Switch - RPU) which will add quite some delay.

The question is if elementary register operations can be speed up by using the PL_LPD connection which directly reaches the Low Power Switch from the PL part?

I saw that the AXI Interconnect on the PL part allows to have multiple Slave connections but it was unclear for me, how the access would differ for these two connections (one via FPD for A53 and one via LPD for R5). In the address editor, there was also no possibility to give a separate address for the access using LPD. How is this configured properly and is this even the right way to go of both A53 and R5 should be able to read/write efficiently from AXI Registers?

Thank you for your input!

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