03-02-2017 05:17 AM
It's been a while, but now I'm back with a new Zynq-7000 project that requires an SPI bus with multiple slaves attached. The SPI core of the Zynq-7000 has 3 Slave Selects available and with the two SPI cores I can address 6 separate slaves. This is enough for me, but I really want to use just the one SPI core and make use of what is mentioned in the TRM: Externally expand the Slave Selects.
This is mentioned in a couple of places in the TRM (Slave select signals can be connected directly to slave devices or expanded externally), but I have failed to find any information about how this is supposed to be done. Since I will be routing the SPI bus through EMIO I could of course use a couple of GPIO and implement a demux in PL, but is there a neater way?
03-02-2017 06:05 AM
I might have stumbled on the answer myself, browsing the register details section of the TRM. Seems there is a mode bit called "PERI_SEL", not much described but from what is there one might suspect that this is in fact the magic bullet: "Peripheral select decode, 1: allow external 3-to-8 decode, 0: only 1 of 3 selects".
I got a little worried though, reading about the config bits "CS" in the same register. It says these bits are only valid in Manual CS mode, but that would imply that Automatic CS mode is only possible in a single slave scenario? Otherwise, how would you control which slave gets picked if not by pointing it out with the CS bits?
Seems every answer gives rise to a couple of new questions, but hopefully there is someone out there with ALL the answers! At least regarding the SPI controller...
03-05-2017 11:45 PM
In Master Mode, the SPI can transfer to and from slaves that are connected to SPI. The slave select pins can be configured to enable different slaves. The way the PERI_SEL bit works is that when PERI_SEL is set to “0”, it will select only one of the selects is active. When the PERI_SEL is set to “1”, the peripheral select signals are output directly. This will enable a 3-bit to 8-bt decoder to be connected externally to provide capability of generating 8 chip selects.
Depending on the peri-sel bit, the chip select lines are output.