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Visitor at93850
Visitor
4,407 Views
Registered: ‎02-18-2013

Zynq 7000 spi fifo tx issue

Hello--

 

I'm having an issue with the onboard SPI port on the Zynq 7000.  Basically, whatever I write to the TX Fifo first stays and never gets overwritten.  Clock looks good, chip select looks good, and the MOSI (I'm the master) line has data on it, it just never changes like it should.  I'm at a loss of what could cause the TX FIFO not to work properly.  I've tried using the manual enable/starts/chip selects to no avail, nothing seems to change the FIFO issue.  Has anyone else ran into this?  Thanks

 

 

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5 Replies
Visitor ehussein
Visitor
4,392 Views
Registered: ‎04-08-2013

Re: Zynq 7000 spi fifo tx issue

No, but, I have run into something different,

 

clock is fine, MOSI is fine,

but the CSb is not.  The width has issue.  from the looks on the scope, it seems to be a pin-strap setting issue.  But it is not.

 

 

u32PinBaseAddr = 0xF8000700;

 

XSpiPs_WriteReg(PinBaseAddr, 0x70,0x22A0); // SCLK

XSpiPs_WriteReg(PinBaseAddr, 0x74,0x02A0); // MISO

// XSpiPs_WriteReg(PinBaseAddr, 0x78,0x32A0); // SSb

XSpiPs_WriteReg(PinBaseAddr, 0x78,0x32A0); // SSb

XSpiPs_WriteReg(PinBaseAddr, 0x84,0x22A0); // MOSI

 

SpiConfig = XSpiPs_LookupConfig(SPI_DEVICE_ID);

XSpiPs_CfgInitialize(SpiInstance, SpiConfig, SpiConfig->BaseAddress);

 

//Enable manual start, enable manual CS mode, no slave selected//Baud rate = clk/ 64, CPOL=0 CPHA=0, enable master mode

XSpiPs_WriteReg(SpiInstance->Config.BaseAddress,0x0,0xFD39);

//Enable the SPI peripheral, and the SS0 pin goes high

XSpiPs_WriteReg(SpiInstance->Config.BaseAddress,0x14,0x0);

XSpiPs_WriteReg(SpiInstance->Config.BaseAddress,0x14,0x1);

 //Assert SS0 pin, SS0 goes low

XSpiPs_WriteReg(SpiInstance->Config.BaseAddress,0x0,0xF939);

XSpiPs_WriteReg(SpiInstance->Config.BaseAddress, 0x1C, 0xAA);

//Trigger Data Transmission

 XSpiPs_WriteReg(SpiInstance->Config.BaseAddress,0x0,0x18039);

//Assert SS0 pin, SS0 goes low

XSpiPs_WriteReg(SpiInstance->Config.BaseAddress,0x0,0xFD39);

 

Perhaps you will share your code, so that I can see how can fix the CSb width issue.

 

Best regards,

EH

 

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Visitor ehussein
Visitor
4,360 Views
Registered: ‎04-08-2013

Re: Zynq 7000 spi fifo tx issue

The issue that I mentioned is related to SSb0 pin in the ES chips.  The problem went away after we switched SSb1 pin.

 

 

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4,034 Views
Registered: ‎10-02-2012

Re: Zynq 7000 spi fifo tx issue

I get somethong similar to what at93850 got :

i write in TX FIFO but when i check if TX FiFO is empty, the TX FIFO never gets empty :Intr_status_reg0 stay to 0. (it should go back to 0x4)  and at the same time see the data set in TXFIFO repeated infinitely on the line.

coud you solve your poproblem an have you any suggestion? 

 

 

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Observer xiaoweihuacom
Observer
3,746 Views
Registered: ‎09-06-2009

Re: Zynq 7000 spi fifo tx issue

 My TX fifo is never empty.

 

do {
StatusReg = XSpiPs_ReadReg(
InstancePtr->Config.BaseAddress,
XSPIPS_SR_OFFSET);
} while ((StatusReg & XSPIPS_IXR_TXOW_MASK) == 0);

 

because TX_FIFO_full(IXR_TXFULL) is always 0, so the program blocked on above code, why xilinx give no reply? 

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Observer dchang3etagen
Observer
61 Views
Registered: ‎07-03-2018

Re: Zynq 7000 spi fifo tx issue

@xiaoweihuacom@at93850@fabien.durand@ehussein

Did anyone ever get this issue resolved?

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