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Zynq DDR ECC error count register never incremented

Moderator
Posts: 7,833
Registered: ‎02-27-2008

Re: Zynq DDR ECC error count register never incremented

a,

 

From the engineer:

 

"The scenario looks okay. In any case if you try to access the un-initialized memory locations you should see non-zero value in the register CHE_ECC_STATS_REG_OFFSET."

 

He did not see your code in your last post, so I will send it to him,

Austin

Austin Lesea
Principal Engineer
Xilinx San Jose
Moderator
Posts: 7,833
Registered: ‎02-27-2008

Re: Zynq DDR ECC error count register never incremented

Try:

 

-   try to make Linux not use all DDR; keep some portion of it reserved for the purposes of this experiment

-   run Linux

-   use XMD to connect to the CPU. This will freeze Linux.

-   from XMD do "mrd <uninitialized_ddr_addr>"

-   read CHE_ECC_STATS_REG_OFFSET now

 

The code you posted no one understands.  It is likely is is not doing anything useful.

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
Observer
Posts: 21
Registered: ‎02-19-2013

Re: Zynq DDR ECC error count register never incremented

Thanks Austin it's good to know my scenario is valid. I can confirm that I don't see this register CHE_ECC_STATS_REG_OFFSET at 0xf80060f0 is always zero hence my concern. In fact I don't think I have ever seen it non-zero....

Observer
Posts: 21
Registered: ‎02-19-2013

Re: Zynq DDR ECC error count register never incremented

That's a brilliant idea Austin - I boot up Linux with the Xilinx JTAG probe connected and fire up XMD and connect to it.

 

I think you want mrd_phys command as the mrd doesn't work because of Virtual Memory (unless you have a way around that).

 

It demonstrates that the register at 0xf80060f0 (CHE_ECC_STATS_REG_OFFSET) is always zero still.

 

XMD% mrd 0xfffffec
ERROR: Cannot Read from target


        Cannot translate from virtual to physical address
        
XMD% mrd_phys 0xfffffec 1
 FFFFFEC:   DEDEDEDE

XMD% mrd_phys 0xf80060f0 1
F80060F0:   00000000

XMD% mrd_phys 0xffffff0 1
ERROR: Cannot Read from target


        AP transaction error (DP CTRL_STAT=0xfc000020)

XMD% mrd_phys 0xf80060f0 1
F80060F0:   00000000

  Note: I have arranged ECC memory to be initialised up to 0xfffffec but not  the next address 0xffffff0. So I can read the early one but get an error on the uninitialised 0xffffff0.

 

But if I write to the uninitialised memory I can read it happily. Note CHE_ECC_STATS_REG_OFFSET always remains zero...

XMD% mwr_phys 0xffffff0 0xdeadbeef
XMD% mrd_phys 0xffffff0 1
 FFFFFF0:   DEADBEEF

XMD% mrd_phys 0xf80060f0 1
F80060F0:   00000000

Observer
Posts: 21
Registered: ‎02-19-2013

Re: Zynq DDR ECC error count register never incremented

Hi Austin, I just had the thought to do this under u-boot instead of Linux - and once you get the exception under u-boot xmd doesn't recover - so basically similar results:

 

 

XMD% connect arm hw

JTAG chain configuration
--------------------------------------------------
Device   ID Code        IR Length    Part Name
 1       4ba00477           4        Cortex-A9
 2       03727093           6        XC7Z020

--------------------------------------------------
Enabling extended memory access checks for Zynq.
Writes to reserved memory are not permitted and reads return 0.
To disable this feature, run "debugconfig -memory_access_check disable".

--------------------------------------------------

CortexA9 Processor Configuration
-------------------------------------
Version.............................0x00000003
User ID.............................0x00000000
No of PC Breakpoints................6
No of Addr/Data Watchpoints.........1

Connected to "arm" target. id = 64
Starting GDB server for "arm" target (id = 64) at TCP port no 1235
XMD% mrd 0xfffffec                                                                                                                                                                 
 FFFFFEC:   DEDEDEDE

XMD% mrd 0xf80060f0 1
F80060F0:   00000000

XMD% mrd 0xffffff0 1
ERROR: Cannot Read from target


        AP transaction error (DP CTRL_STAT=0x0ffff090)
        Error Address = 0x0ffffff0, Size = 0x00000004


XMD% mrd 0xf80060f0 1
ERROR: Cannot Read from target


        AP transaction timeout (ACK=0x01, Expected=0x02)


XMD% mwr 0xffffff0 0xbeefdead
ERROR: Cannot write to target


        AP transaction timeout (ACK=0x01, Expected=0x02)

Observer
Posts: 21
Registered: ‎02-19-2013

Re: Zynq DDR ECC error count register never incremented

Hi no reply today - on holiday?

 

Andrew

Moderator
Posts: 7,833
Registered: ‎02-27-2008

Re: Zynq DDR ECC error count register never incremented

Nope,

 

I'm here.  I have passed it along, and passed back their suggestion.  They have verified it, and it works.

 

I suggest you file a webcase (in fact, you should have done that first if this is something that is preventing you from getting your design done).  The forums are useful, but there is not time clock on them, and no one has to answer.

 

We discovered that we had not enabled the parity error interrupt on the L1 in some test code we were running recently.  Like most really difficult software bugs, it took over a month to find it.

 

In theory it all works.  In characterization it is all working.  In practice one has to write code (and perhaps depend on other code, too).

Austin Lesea
Principal Engineer
Xilinx San Jose
Observer
Posts: 21
Registered: ‎02-19-2013

Re: Zynq DDR ECC error count register never incremented

I already have a web case - 964504 - still awaiting a response to my offer of three options on how to proceed.

 

I think in practise the only thing that counts is working code and how do we know the code is working if we can't test it ...

 

That said I think you already told me that "people have tested it and it works" but can they tell me how to use the registers to test ECC?

 

Or is that secret magic stuff and they don't think it is needed by Xilinx customers?

 

Even better would be to supply me with their working code and I can check it for my self....

 

 

Thanks

 

Moderator
Posts: 7,833
Registered: ‎02-27-2008

Re: Zynq DDR ECC error count register never incremented

Email the link to this thread back to support with your case number,

 

If the response is slow (lacking), request the case be escalated.


You are the customer, hence, you are always right.

 

No need to passively wait for a support response!

 

If you are not asking, the person handling your case is likely to assume you found your problem and went away....don't let that happen.

 

Austin Lesea
Principal Engineer
Xilinx San Jose
Observer
Posts: 21
Registered: ‎02-19-2013

Re: Zynq DDR ECC error count register never incremented

Is anyone working on this issue?

 

I have uploaded a SD card image on the web case 964504 :

https://xapps11.xilinx.com/amdocs_prod/eSupport/eSupportJSP/CaseShow.jsp?id_number=964504

 

which contains details and files that allow you to reproduce the issue under Linux on a Zedboard.

 

So the question remains "How do you verify ECC RAM works on the Zync chip?"