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Visitor elliotr
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7,385 Views
Registered: ‎09-08-2014

Zynq PS PL Interface

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So, somewhat n00b question. I've been poring over what it takes to get the PS to communicate with the PL on the Zedboard. I keep hearing AXI mentioned, but am not sure how I set it up. When I'm looking through the options in the IP catalog, I don't really know what to use (I'm using vivado 2014) to get this going. All of the tutorials and explanation I find seem to have to do with peripherals, which is not what I'm trying to do, or all too in-depth for me to get.

Basically I'm looking for a way to send a few bytes to the PL that tell it to initiate or terminate an analog signal (I've already taken care of outputting that signal, so that's out of the equation), and a couple of parameters associated with that signal. The PL in question will probably be clocking a lot slower than the PS.

Since I don't really know what I'm doing, the simplest explanation would be the best.

thanks.

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Teacher muzaffer
Teacher
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Registered: ‎03-31-2012

Re: Zynq PS PL Interface

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This is quite easy actually. What you need is actually a peripheral. In vivado go to Tools|Create&PackageIP|Create New IP. There click OK to all the buttons which will give you a axi lite slave peripheral which has 4 registers which can be controlled from the PS. You even get software drivers etc.
The only thing you have to do extra is to edit the myip_v1_0_S00_AXI.v file (if you kept the original names) to connect your AFE signals to slv_regX wires. You can do this by either instantiating your AFE controller in that module or you can export the slv_reg_X signals out of it and connect them elsewhere.

You can also watch this video: https://www.youtube.com/watch?v=31DtYApASRo

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Adventurer
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Registered: ‎01-10-2014

Re: Zynq PS PL Interface

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Hello, elliotr,

I think you should check some example reference design (for example from here: http://wiki.analog.com/resources/fpga/xilinx/kc705/adv7511) and see how they connect the PS to axi_interconnect cores. It's easier than it seems to be.
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Teacher muzaffer
Teacher
10,358 Views
Registered: ‎03-31-2012

Re: Zynq PS PL Interface

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This is quite easy actually. What you need is actually a peripheral. In vivado go to Tools|Create&PackageIP|Create New IP. There click OK to all the buttons which will give you a axi lite slave peripheral which has 4 registers which can be controlled from the PS. You even get software drivers etc.
The only thing you have to do extra is to edit the myip_v1_0_S00_AXI.v file (if you kept the original names) to connect your AFE signals to slv_regX wires. You can do this by either instantiating your AFE controller in that module or you can export the slv_reg_X signals out of it and connect them elsewhere.

You can also watch this video: https://www.youtube.com/watch?v=31DtYApASRo

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Visitor elliotr
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Registered: ‎09-08-2014

Re: Zynq PS PL Interface

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I'm trying to do this (Tools|Create&PackageIP|Create New IP -> Create a new AXI4 peripheral) but every time I try I get vivado internal exception that make buttons disappear. Is that what you were suggesting? (minus the exceptions. I'm looking into that right now.)
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Teacher muzaffer
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Registered: ‎03-31-2012

Re: Zynq PS PL Interface

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Yes, that's what I am suggesting. Once you fix your exception issue, create an AXI lite peripheral and add your analog block to it.

As to your exception, which OS are you using? You might want to try a supported linux version if yours isn't.
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Visitor elliotr
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Registered: ‎09-08-2014

Re: Zynq PS PL Interface

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Fixed the exception issue. it was this bug: http://www.xilinx.com/support/answers/60477.html
so I made a placeholder ventor name, and also upgraded vivado 2014.3
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Visitor elliotr
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Registered: ‎09-08-2014

Re: Zynq PS PL Interface

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this looks like it should do the trick. Now how do I figure out how I tell the processor to send things to this...?
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Teacher muzaffer
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Registered: ‎03-31-2012

Re: Zynq PS PL Interface

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checkout the software drivers which are generated by the "create ..." .
basically the slave's registers are memory mapped ie a write to a specific address decided by the base address of the slave when you instantiate it in your block design and the offset of the register. you either write to that address (bare metal) or you mmap that address and write to the virtual address you get (linux). what ever data you write appears in the register you write to. If you want to pulse you can generate one either on the write transaction itself or decode the value of the register and generate a pulse on 0-1 transition (if you want a short pulse).
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Visitor elliotr
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Registered: ‎09-08-2014

Re: Zynq PS PL Interface

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I see. and the AXI master can poll those registers from the slave, right?

also thanks for all the help so far!
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Teacher muzaffer
Teacher
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Registered: ‎03-31-2012

Re: Zynq PS PL Interface

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yes AXI master (in this case the processor) can poll those registers. Of course making your slave return values other than slv_reg_x stuff is a little more involved in the changes necessary to the myip_v1_0_S00_AXI module
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Visitor elliotr
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Registered: ‎09-08-2014

Re: Zynq PS PL Interface

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okay, that's fair.
Also, I still haven't found the "create ..." option you're talking about. Where can I find that, and the software driver?
Again, I'm sorry, I'm kind of new to this.
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Teacher muzaffer
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Registered: ‎03-31-2012

Re: Zynq PS PL Interface

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Open Vivado, open or create a project, then tools menu, create & package new ip, create new axi4 peripheral, click next on every tab. The ip is created in a directory called ip_repo in the same directory as your project. Browse the files therein.
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Visitor elliotr
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Registered: ‎09-08-2014

Re: Zynq PS PL Interface

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I've found the driver files, but the .c file is basically empty. Does it get populated later?
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Teacher muzaffer
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Registered: ‎03-31-2012

Re: Zynq PS PL Interface

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yep, by you :-)

checkout the myip_selftest.c file which shows how to do basic access.
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