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Observer sasisaketh
Registered: ‎09-23-2016

Zynq Power down sequencing



In my application, there is no requirement for powering the device OFF. But, during design and testing we will need to power cycle the device a few hundred times which necessitates the need to follow the turn OFF sequence. However, we were unable to meet the Zynq power down sequencing requirements for both PS and PL due to board design constraints. The power up sequencing is taken care off. I have gone through AR# 65240 and AR# 63149, but was unable understand the impact of not following power down sequencing with respect to IO pin states . Also note that we are not using encryption or authentication in our design, in this scenario should we be bothered about the PS eFuse. 


Design Details :

1 > I have a set of converters that take in power at 5V and provide me with 1.0V, 1.8V, 3.3V and 0.9 VTT in the same order (PG of one converter is connected to the EN of the next converter) - for power up sequencing.

2 > I cannot afford to have a separate sequencing logic for power down sequencing, but I can turn OFF the 5V supply, thereby turning OFF all the powers at the same time.

3 > I am using a bleeder resistor at the output of my power supplies to ensure quick discharge of converter output capacitors after turn-OFF. The load capacitance each converter is seeing is in the following increasing order - 0.9V, 3.3V, 1.8V and 1.0V. Since the capacitances are in this order, does having a bleeder resistor take care of the power OFF sequence? as I assume, the lowest load capacitance will discharge fastest, thereby turning OFF first.


Please let me know if this can work.





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Scholar austin
Registered: ‎02-27-2008

Re: Zynq Power down sequencing



The only hard requirement (you must observe) is: (page 5, ds181) (as you do not use efuses).


For VCCO voltages of 3.3V in HR I/O banks and configuration bank 0:
• The voltage difference between VCCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each
power-on/off cycle to maintain device reliability levels.
• The TVCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps.


The time is 800 ms at 85 C (not to exceed).  A resistor to drop the 3.3v Vcco is all you may need.  You may not need it at all (you might not be in this condition at all, or for much less that 800 ms).


This is for the ARTIX 7 FPGA device family, with is used for the PL in (smaller) Zynq devices.  There is a similar requirement for the larger Zynq devices based on Kintex 7 FPGA PL.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Xilinx Employee
Xilinx Employee
Registered: ‎10-11-2011

Re: Zynq Power down sequencing

65240 - Design Advisory for Zynq-7000 AP SoC: Power-On/-Off Sequence Requirements for PS eFUSE Integrity

is relevant even if you are not planning to use AES and/or RSA.

Be sure to meet those power down requirements for your Zynq-7000 device.

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