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Visitor vova2211
Registered: ‎08-06-2017

Zynq UltraScale+ MPSoC LPD POR FUnctionality

Dear community,

I'm planing to power on my Zynq UltraScale+ device first in Low Power (LPD) state when only RPUs are operating. And later, on the RS232 command, it should switch over to the FPD+PL state. Currently I'm confused how should i manage the Reset inputs to device in LPD and FPD states  :


1. The PS_POR_B input, can it be asserted high when only LPD domain powered ?

2. In switching from LPD to FPD+PL - should I toggle the POR again or it releases the FPD itself by internal por supply supervising?



According to :


PS Power-On/Off Power Supply Sequencing

The low-power domain (LPD) must operate before the full-power domain (FPD) can function. The

low-power and full-power domains can be powered simultaneously. The PS_POR_B input must be asserted

to GND during the power-on sequence (see Table 37). The FPD (when used) must be powered before

PS_POR_B is released.

  • Means POR can't be asserted high in LP state, while FPD supplies are off.


and according to :


The power-on reset (POR) block in the PS deasserts the reset signal to the LPD (CRL) and the

FPD (CRF) clock and reset blocks when the PS power is stable.

  • Means that POR may be asserted high in LP state to release the LP from reset, before the FPD supplies powered on.

Which one is correct ?






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