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Observer dchang3etagen
Observer
54 Views
Registered: ‎07-03-2018

Zynq UltraScale+ MPSoC : PS SPI behavior different between SDK and SDcard boot

I am on the Zynq UltraScale+ MPSoC ZCU102 with 2018.1.  I'm trying to debug an issue with the PS SPI.  The behavior is different between SDK debug and SDcard boot.

I have routed SPI0 using EMIO through the FPGA onto the J3 header pins.

 

When I run my R5 application using the SDK debugger, the SPI module functions normally and I can see CS0, CLK and MO activity on the J3 header pins.

 

If I run my R5 application using remoteproc from petalinux using SDcard boot, I can only see CS0 activity on the J3 header pins.  It seems that the TX FIFO never empties and no data is sent, so no activity on CLK or MO.  The ISR register shows TX_FIFO_not_full=0 and TX_FIFO_full=1.

 

Here are the SPI configuration values-

SPI_ref_clk is 200Mhz

FIFO threshold is 1

SPI0 config = 0x27829 (Master, Mode0, DIV64, Manual CS, CS0)

 

My code sequence is-

0) reset and disable SPI0

1) configure SPI0 and set CS

2) enable SPI0

3) write to SPI0 TX_data

4) poll SPI0 ISR (gets stuck here when running from SDcard boot)

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Observer dchang3etagen
Observer
34 Views
Registered: ‎07-03-2018

Re: Zynq UltraScale+ MPSoC : PS SPI behavior different between SDK and SDcard boot

I think I identified the issue.

For some reason, when the CRL_APB SPIn_REF_CTRL registers are configured during SDcard boot, the clock settings are updated but the clock is left disabled.

The values are changed from default to match the Vivado settings but the SPI clock enable bit is left disabled.

Is this a bug?

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