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Observer dchang3etagen
Observer
131 Views
Registered: ‎07-03-2018

Zynq UltraScale+ MPSoC SPI - No output

I'm trying to use the SPI module via EMIO output through the FPGA routed to the pins on header J3.

 

I am able to see the CS lines toggle based on my SPI configuration.

I am able to write to the TX FIFO and see the TX_FIFO_not_full and TX_FIFO_full bits change appropriately in the ISR register.

However, I do not see any activity on the CLK and MO pins on J3 (constanly low).

I have tried full Master Auto mode, Master with manual CS, and Master with manual CS and manual Start.  In all cases, there is no output.

 

In my FPGA design I have-

spi0_ss_i_n tied to a Constant block set to output 1

spi0_s_i tied to a Constant block set to output 0

spi0_sclk_i tied to a Constant block set to output 0

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7 Replies
Xilinx Employee
Xilinx Employee
109 Views
Registered: ‎09-01-2014

Re: Zynq UltraScale+ MPSoC SPI - No output

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Observer dchang3etagen
Observer
97 Views
Registered: ‎07-03-2018

Re: Zynq UltraScale+ MPSoC SPI - No output

@ritakur

Thanks for the link to AR 69276.

I already tried configuring my FPGA design as described, without using the Constant blocks (such as Constant 1 input to spi0_ss_i_n).

However, it resulted in the same condition - no MO output was seen on the pin, only CS0,1,2 was changing and TX FIFO remained Full.

You can see my FPGA design pictures attached.  The pins connect directly to the ports with nothing in between.  My plan was to connect SPI0 and SPI1 externally using jumper wires on the J3 pins.  The J3 pinout is also attached (from UG1182).

Here are the constraints settings I used-

set_property DRIVE 12 [get_ports {gpio_proto_hdr[0]}]
set_property DRIVE 12 [get_ports {gpio_proto_hdr[1]}]
set_property DRIVE 12 [get_ports {gpio_proto_hdr[2]}]
set_property DRIVE 12 [get_ports {gpio_proto_hdr[3]}]
set_property DRIVE 12 [get_ports {gpio_proto_hdr[4]}]
set_property DRIVE 12 [get_ports {gpio_proto_hdr[5]}]
set_property DRIVE 12 [get_ports {gpio_proto_hdr[6]}]
set_property DRIVE 12 [get_ports {gpio_proto_hdr[7]}]
set_property DRIVE 12 [get_ports {gpio_proto_hdr[8]}]
set_property DRIVE 12 [get_ports {gpio_proto_hdr[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_proto_hdr[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_proto_hdr[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_proto_hdr[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_proto_hdr[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_proto_hdr[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_proto_hdr[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_proto_hdr[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_proto_hdr[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_proto_hdr[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_proto_hdr[9]}]
set_property SLEW SLOW [get_ports {gpio_proto_hdr[0]}]
set_property SLEW SLOW [get_ports {gpio_proto_hdr[1]}]
set_property SLEW SLOW [get_ports {gpio_proto_hdr[2]}]
set_property SLEW SLOW [get_ports {gpio_proto_hdr[3]}]
set_property SLEW SLOW [get_ports {gpio_proto_hdr[4]}]
set_property SLEW SLOW [get_ports {gpio_proto_hdr[5]}]
set_property SLEW SLOW [get_ports {gpio_proto_hdr[6]}]
set_property SLEW SLOW [get_ports {gpio_proto_hdr[7]}]
set_property SLEW SLOW [get_ports {gpio_proto_hdr[8]}]
set_property SLEW SLOW [get_ports {gpio_proto_hdr[9]}]
set_property PACKAGE_PIN H14 [get_ports {gpio_proto_hdr[7]}]
set_property PACKAGE_PIN J14 [get_ports {gpio_proto_hdr[6]}]
set_property PACKAGE_PIN G14 [get_ports {gpio_proto_hdr[5]}]
set_property PACKAGE_PIN G15 [get_ports {gpio_proto_hdr[4]}]
set_property PACKAGE_PIN J15 [get_ports {gpio_proto_hdr[3]}]
set_property PACKAGE_PIN J16 [get_ports {gpio_proto_hdr[2]}]
set_property PACKAGE_PIN G16 [get_ports {gpio_proto_hdr[1]}]
set_property PACKAGE_PIN H16 [get_ports {gpio_proto_hdr[0]}]
set_property PACKAGE_PIN G13 [get_ports {gpio_proto_hdr[8]}]
set_property PACKAGE_PIN H13 [get_ports {gpio_proto_hdr[9]}]

 

Here is the ports and mapping for SPI signals to gpio_proto_hdr-

gpio_proto_hdr : inout STD_LOGIC_VECTOR ( 9 downto 0 );

spi_clk : out STD_LOGIC;
spi_mo : out STD_LOGIC;
spi_cs0 : out STD_LOGIC;
spi_cs1 : out STD_LOGIC;
spi_cs2 : out STD_LOGIC;
spi_so : out STD_LOGIC;
spi_clk_in : in STD_LOGIC;
spi_mi : in STD_LOGIC;
spi_si : in STD_LOGIC;
spi_cs0_in : in STD_LOGIC

spi_clk => gpio_proto_hdr(0), -- SPI CLK
spi_clk_in => gpio_proto_hdr(1), -- SPI CLK in
spi_mo => gpio_proto_hdr(2), -- SPI MO
spi_si => gpio_proto_hdr(3), -- SPI SI
spi_mi => gpio_proto_hdr(4), -- SPI MI
spi_so => gpio_proto_hdr(5), -- SPI SO
spi_cs0 => gpio_proto_hdr(6), -- CS0
spi_cs0_in => gpio_proto_hdr(7), -- CS0 in
spi_cs1 => gpio_proto_hdr(8), -- CS1
spi_cs2 => gpio_proto_hdr(9), -- CS2

Here are the SPI configuration values-
SPI0 config = 0x27829 (Master, Mode0, DIV64, Manual CS, CS0)

SPI1 config = 0x20028 (Slave, Mode0, DIV64)

 

 

SPI_EMIO_pins.png
SPI_ports_out.png
SPI_ports_in.png
J3_pins.png
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Observer dchang3etagen
Observer
81 Views
Registered: ‎07-03-2018

Re: Zynq UltraScale+ MPSoC SPI - No output

I verified that I am able to see th CS output on all of the J3 header pins. So I do not think the issue is related to the FPGA setup. 

 

The main issue I see is that the SPI module seems to never “turn on” and transmit data from the TX FIFO. The TX FIFO just gets filled up and never empties. As a result, no output is seen on the MOSI

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Observer dchang3etagen
Observer
79 Views
Registered: ‎07-03-2018

Re: Zynq UltraScale+ MPSoC SPI - No output

Here are the SPI configuration values-

SPI_ref_clk is 200Mhz

FIFO threshold is 1

SPI0 config = 0x27829 (Master, Mode0, DIV64, Manual CS, CS0)

 

My code sequence is-

0) reset and disable SPI0

1) configure SPI0 and set CS

2) enable SPI0

3) write to SPI0 TX_data

4) poll SPI0 ISR (TX FIFO always full, never not full)

 

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Observer dchang3etagen
Observer
53 Views
Registered: ‎07-03-2018

Re: Zynq UltraScale+ MPSoC SPI - No output

I am going to close this thread (if I can) as I have confirmed that there is no issue with my SPI driver code or the FPGA design.

The same code and FPGA works when executed using the SDK but does not work when booting from an SD card and executed through remoteproc.

So my issue is somehow related to the difference in how the overall system is configured/initialized/setup between SDK vs SDcard+remoteproc.

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Scholar watari
Scholar
46 Views
Registered: ‎06-16-2013

Re: Zynq UltraScale+ MPSoC SPI - No output

Hi @dchang3etagen

 

I guess you don't execute PMU firmware when you do debug your code by SDK.

If yes, I'm probably sure the behaivor is by design...

 

Best regards,

 

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Observer dchang3etagen
Observer
44 Views
Registered: ‎07-03-2018

Re: Zynq UltraScale+ MPSoC SPI - No output

Hi @watari

With the SDK debugger, I run only the R5 binary.

Do you have a suggestion about the cause of the problem?  Where should I look?

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