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Contributor
Contributor
981 Views
Registered: ‎11-10-2017

Zynq can't receive data from DMA by using AXI4-Stream

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I am new to Zynq.

I am trying to make design using AXI4-Stream between PS and PL.

I have read some User Guide, but I couldn’t understand why my design doesn’t work correctly.

I high-level synthesized the following code on Vivado HLS

 

void example(int A[50], int B[50]){

#pragma HLS INTERFACE axis port=A

#pragma HLS INTERFACE axis port=B

              int i;

              for(i = 0; i < 50; i++){

                            B[i] = A[i] + 5;

              }

}

I made design like an attachment. (I referred the course of George Mason University, http://ece.gmu.edu/coursewebpages/ECE/ECE699_SW_HW/S15/tutorials/Tutorial_AXI-Stream_HLS_IP.pdf )

 

After I generate bitstream, I build the Application Project on SDSoC.

I used helloworld template and rewrote “helloworld.c” to the code as the following link

  http://ece.gmu.edu/coursewebpages/ECE/ECE699_SW_HW/S15/tutorials/tutorial_4_files/example_c_code.c

 

I build the project, and run on ZYBO.

The result is the following.

 

Error : RxBuffer[0] = 0

Error : RxBuffer[1] = 0

Error : RxBuffer[2] = 0

Error : RxBuffer[3] = 0

Error : RxBuffer[4] = 0

Error : RxBuffer[5] = 0

RxBuffer[6] = 11

RxBuffer[7] = 12

RxBuffer[8] = 13

RxBuffer[9] = 14.

 

The first 5 values of the beginning is wrong.

I have two questions.

 

1) What’s wrong with my design or application code?

  For the purpose of debug, I inserted the code, "while (XAxiDma_Busy(&AxiDma, XAXIDMA_DEVICE_TO_DMA)) {};", after "Status = XAxiDma_SimpleTransfer(&AxiDma,(u32) RxBuffer, BYTES_TO_TRANSFER, XAXIDMA_DEVICE_TO_DMA);". Then, it caused endless loop. Why is DMA remained busy?

 

2) We can use “ap_ctrl_none” directive on Vivado HLS, and according to user guide, “When the interface protocol ap_ctrl_none is used, no block-level I/O protocols are added to the design. The only ports are those for the clock, reset and the data ports.”

 So, if we use ap_ctrl_none directive, how can we control ap_start ? Has ap_start been fixed at 1?

 

 

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スクリーンショット 2017-11-14 13.06.31.png
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1 Solution

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Contributor
Contributor
1,148 Views
Registered: ‎11-10-2017

Re: Zynq can't receive data from DMA by using AXI4-Stream

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I solved the problem.

In AXI DMA v7.1 LogiCORE IP Product User Guide, there is following description.

"AXI DMA writes start at the Buffer Address and continues until tlast is received from the streaming side. "

 

So, I have to assert TLAST signal.

In example project from xilinx (https://www.xilinx.com/support/answers/57562.html), I found there is tlast_gen module between S_AXIS_S2MM port of DMA and HW module output port.

 

tlast_gen source is in dma_ex_interrupt/lib/xilinx.com_user_tlast_gen_1.0 directory.

 

I add tlast_gen to my design, and it works correctly!

 

 

 

arrayadd.png
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1 Reply
Contributor
Contributor
1,149 Views
Registered: ‎11-10-2017

Re: Zynq can't receive data from DMA by using AXI4-Stream

Jump to solution

I solved the problem.

In AXI DMA v7.1 LogiCORE IP Product User Guide, there is following description.

"AXI DMA writes start at the Buffer Address and continues until tlast is received from the streaming side. "

 

So, I have to assert TLAST signal.

In example project from xilinx (https://www.xilinx.com/support/answers/57562.html), I found there is tlast_gen module between S_AXIS_S2MM port of DMA and HW module output port.

 

tlast_gen source is in dma_ex_interrupt/lib/xilinx.com_user_tlast_gen_1.0 directory.

 

I add tlast_gen to my design, and it works correctly!

 

 

 

arrayadd.png
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