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Visitor best7467_3
Visitor
4,570 Views
Registered: ‎02-06-2015

Zynq intended use

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  I need clarification on the intended use of Zynq series chips.  I need to have an FPGA based system for data aquisition in which minimizing the latency into and out of the fabric is the most important design goal.  Digital filtration using IIR filters is needed and the coefficients for those filters need to be adjustable by the user.  The incoming data will be filtered and sent back out of the device with DACs.  The DACs need to interface with analog circuits that will affect the incoming data stream.  My first thought was to use the ARM cores of the Zynq chip to update the filter coefficients and also to stream the final data to a PC.  But, looking at the AXI IP in Vivado, there does not appear to be a way to "break-out" the signals from the AXI data lines in order to interface directly with custom logic that runs autonomously relative to the ARM cores.  I have tried numerous ways to do this in Vivado while reading all of the availble data sheets, tech notes and online tutorials.  I have read and re-read many forum posts without this issue being covered.  I know that you can create an AXI custom peripheral and insert your code in line with the AXI stream.  But, I do not think this will be workable for my system.  My interpretation is that the Zynq chips are meant to be used with all transactions routed through the ARM cores.  This unfortunately will not work for my application.  Am I missing something?  Should I use a standalone FPGA with a separate floating point processor and simply bring the coefficients to the FPGA via QSPI? 

 

Thank you,

Aaron

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Scholar austin
Scholar
7,828 Views
Registered: ‎02-27-2008

Re: Zynq intended use

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A,

 

Sounds like you have a conventional signal processing application:  data in to process, data processed goes out.  That flow is suited to the Vivado IP integrator flow:  select the blocks to perform your processing, ignoring the processor system.  Then,, at the end, add the processor system to load coeffients into the filters through the general purpose, low speed AXI bus (add a GPIO block to allow control an coefficient loading).

 

Yes, a 'plain' FPGA device would also work, but the updating of coefficients would likely require the addition of a MicroBlaze, and whatever peripherals and memories you require.  Zynq provides all the processing, and peripherals, so there is less to do, and the processor side is more powerful (you may decide to run Linux just because that allows so much flexibility).

 

Obviously the processor is not in the data flow processing path (only used to control it).  Another approach to data flow designs is System Generator flow.

 

Floating point operations in the data path will not run as fast as integer based elements, and will use more DSP blocks and logic to realize.

 

If the floating point processors in the ARM processor in Zynq are fast enough, and using the AXI Stream interfaces with the HP bus (high performance) allow it to get data, process it in a c program using the floating point operations, then that is also a flow (again using IP Integrator) that woulkkd work, but it will never be as fast as staying within the FPGA fabric for the entire datapath.

 

The good news is that you have many options with Zynq:  if one does not meet the goals, another will.

Austin Lesea
Principal Engineer
Xilinx San Jose
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3 Replies
Scholar austin
Scholar
7,829 Views
Registered: ‎02-27-2008

Re: Zynq intended use

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A,

 

Sounds like you have a conventional signal processing application:  data in to process, data processed goes out.  That flow is suited to the Vivado IP integrator flow:  select the blocks to perform your processing, ignoring the processor system.  Then,, at the end, add the processor system to load coeffients into the filters through the general purpose, low speed AXI bus (add a GPIO block to allow control an coefficient loading).

 

Yes, a 'plain' FPGA device would also work, but the updating of coefficients would likely require the addition of a MicroBlaze, and whatever peripherals and memories you require.  Zynq provides all the processing, and peripherals, so there is less to do, and the processor side is more powerful (you may decide to run Linux just because that allows so much flexibility).

 

Obviously the processor is not in the data flow processing path (only used to control it).  Another approach to data flow designs is System Generator flow.

 

Floating point operations in the data path will not run as fast as integer based elements, and will use more DSP blocks and logic to realize.

 

If the floating point processors in the ARM processor in Zynq are fast enough, and using the AXI Stream interfaces with the HP bus (high performance) allow it to get data, process it in a c program using the floating point operations, then that is also a flow (again using IP Integrator) that woulkkd work, but it will never be as fast as staying within the FPGA fabric for the entire datapath.

 

The good news is that you have many options with Zynq:  if one does not meet the goals, another will.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Teacher muzaffer
Teacher
4,557 Views
Registered: ‎03-31-2012

Re: Zynq intended use

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You can certainly design your datapath in PL portion which receives data from an ADC, processes it with some weights and sends them out to a DAC. In parallel you can have an AXI slave which accepts and stores the previously mentioned weights for the datapath to use. There is no requirement for data to percolate to ARM cores. It is entirely possible to use the ARM cores as a high level controller which sets certain values (weights, coefficients etc) in the PL through a relatively slow interface and let the PL do the heavy lifting in terms of datapath.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Visitor best7467_3
Visitor
4,546 Views
Registered: ‎02-06-2015

Re: Zynq intended use

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Thank you both, Austin and Muzaffer.

 

This is good news.  I will follow your suggestions and perhaps follow up with questions.

 

Best regards,

Aaron

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