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ZynqMP as PCie endpoint host access to DMA registers

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Posts: 16
Registered: ‎01-29-2015

ZynqMP as PCie endpoint host access to DMA registers

Hi Forum,

 

I am struggling with the access to the DMA configuration registers from the host PC.

 

I wrote an embedded Linux driver to initialize and setup the ingress windows in the AXI to PCIe bridge on the ZynqMP. I also have a FSBL which initializes the PCIe core. 

 

I can successfully read and write from my memory bars with a dedicated Windows and Linux driver.

When I try to access the DMA registers in the memory bar marked as "Bridge bar Indicator" in Vivado I get only zeros.

 

The register BRIDGE_CORE_CFG_PCIE_RX0 is automatically set to 0x00010004. Which seems correct to me.

 

I need some clarification on the following questions:

 

1) When the "Bridge bar Indicator" memory bar is access by the host the read/write is automatically redirected to the address 0xFD0F0000 ?

 

2) No Ingress Window needs to be configured to allow access to the DMA registers ?

 

3) Does the memory bar used as "Bridge bar Indicator" require specific parameters ?

(See attached screen shot PCIe_BAR_Settings.jpg)

 

4) Actually most of the DMA registers seem to be zero by default. At least I should see the default value 0x00008000 at 

DMA_CHANNEL_DMA_STATUS 0xFD0F007C

 

5) When I write a pattern to SCRATCH0 (0xFD0F0050) from within the device it should be visible in the host memory bar (no caching involved)?

 

6) Does accessing the DMA register depend on the type of hardware in use ?

I am using an UltraZED evaluation board.

 

 

Thanks

Martin

 

 

PCIe_BAR_Settings.JPG