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Observer duckcud
Observer
4,848 Views
Registered: ‎02-27-2014

control the fabric clocks fclk through Zynq PS in standalone mode

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Hello Experts,

 

is it possible to control the fabric clock (fclk_clk[0...3]) through PS processor without linux integrated? I wanna activate and deactivate the fclk to freeze and release PL design by a bare-metal application. Is that possible?

 

Thank you in Advance!

 

Best Regards,

YM 

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Teacher muzaffer
Teacher
9,181 Views
Registered: ‎03-31-2012

Re: control the fabric clocks fclk through Zynq PS in standalone mode

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these are initially controlled with the fsbl anyway so you definitely don't need linux. With bare metal you can access the registers controlling these clocks. Read the zynq TRM ug585 specifically register FPGA0_CLK_CTRL and other related ones.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Scholar austin
Scholar
4,836 Views
Registered: ‎02-27-2008

Re: control the fabric clocks fclk through Zynq PS in standalone mode

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Yes,

 

You can do this in a bare metal design.  I would send these to the PL (always), and the use an AXI GPIO core to enable/disable the global clock buffers in the fabric (programmable logic - PL).  That way, your bare metal program uses the GPIO to control the PL clocks.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Teacher muzaffer
Teacher
9,182 Views
Registered: ‎03-31-2012

Re: control the fabric clocks fclk through Zynq PS in standalone mode

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these are initially controlled with the fsbl anyway so you definitely don't need linux. With bare metal you can access the registers controlling these clocks. Read the zynq TRM ug585 specifically register FPGA0_CLK_CTRL and other related ones.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
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Observer duckcud
Observer
4,735 Views
Registered: ‎02-27-2014

Re: control the fabric clocks fclk through Zynq PS in standalone mode

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Hi muaffer,

 

thank you so much! That's it!

But there is a mistake in the TRM file. The disable and enable should be written in the FPGAx_THR_CNT register not _CTRL. Hope that the xilinx stuff can update this mistake.

Screen Shot 2016-09-28 at 13.14.51.png

 

BRs, YM

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