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Participant lizhang86
Participant
194 Views
Registered: ‎04-25-2017

gem external fifo tx_r_rd stuck low

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Hello,

I want to access gem through external FIFO.  The tx_r_rd would go high after tx_r_data_rdy is set, but it would be stuck low after 8 clock cycles.  There is no status signal to indicate an error.  More detail is in the attached ila capture.  I cannot find any relevant debug information regarding this issue in ug1805.  Any help would be appreciated.  

Thanks,

Li 

tmp.jpg

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Participant lizhang86
Participant
171 Views
Registered: ‎04-25-2017

Re: gem external fifo tx_r_rd stuck low

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Hello,

I solved my problem by enabling the external_fifo_interface register in GEM (0xff0e004c for gem3) using mwr. Apparently, it is not enough to just select external fifo interface for gem in the block design.  The external_fifo_interface register must also be enabled during software configuration.  These procedures to enable external fifo mode for gem are not documented in TRM.

 

Best Regards,

Li 

 

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Participant lizhang86
Participant
172 Views
Registered: ‎04-25-2017

Re: gem external fifo tx_r_rd stuck low

Jump to solution

Hello,

I solved my problem by enabling the external_fifo_interface register in GEM (0xff0e004c for gem3) using mwr. Apparently, it is not enough to just select external fifo interface for gem in the block design.  The external_fifo_interface register must also be enabled during software configuration.  These procedures to enable external fifo mode for gem are not documented in TRM.

 

Best Regards,

Li 

 

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