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Explorer
Explorer
941 Views
Registered: ‎09-15-2011

loss package between PL and PS

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Hi all,

I have a questoion about how to transfer the bram data in PL to PS DDR,

the detail is,

from the Front-end, we have one Channel ADC,and get the package data(the data size is 1024*16bit), in the PL side ,I use two block ram, PS read one and the other wrote by PL。

there are two methods get the data from PL to PS

1: GP port, in the project, we use the AXI-Bram-controller connect the bram PORT A, and PL write B,and instance axi-gpio(full flag about the bram), in linux, we read the full flag through the axi-gpio , if full flag is true, we use the memory copy function to copy the package data from PL to PS DDR, when we use this way ,some packages are loss, in our system , this way is false. maybe the linux is slow ,and the PL is fast

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Xilinx Employee
Xilinx Employee
1,182 Views
Registered: ‎11-30-2007

Re: loss package between PL and PS

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You can use the HP port for direct access to the PS-DDR memory.  You can use the AXI DMA to transfer the data from your PL source.

 

PS-to-PL DMA.jpg

 

If you use the AXI DMA in Simple DMA mode, the important registers are as follows.  There are 3 registers for Source and 3 registers for Destination (depending on direction of DMA).

 

AXI_DMA Registers.jpg

 

Assuming the following Memory Map:

 

DDR "Source" Address: 0x0011_0000
DDR "Destination" Address: 0x0012_0000
MM2S Source
0x4040_0000 : MM2S DMA Control Register
0x4040_0018 : MM2S Source Address (31:0) Register
0x4040_0028 : MM2S Source Length Register
S2MM Destination
0x4040_0030 : S2MM DMA Control Register
0x4040_0048 : S2MM Destination Address (31:0) Register
0x4040_0058 : S2MM Destination Length Register

 

You can use the XSCT Console (in SDK) to write to the Source Addresses (data to send to PL) and to read the Destination Addresses (to verify data from PL).  For example, use the following commands from XSCT to write specific data to the Source Address and verify the data was written as expected:

 

mwr -size w 0x00110000 {0x01234567 0x12345678 0x23456789 0x34567890 0x45678901 0x56789012 0x67890123 0x78901234 0x89012345 0x90123456 0x21436587 0xffeeddcc} 0x100
  Write 256 words starting at address 0x0011_0000 & fill with list with remaining filled by last value

 

mrd 0x00110000 0x100
  Read 256 (0x100) words starting at address 0x0011_0000

 

For DMA Transfer from PS-DDR to PL and then from PL to PS-DDR:

 

DMA Transfers begin with the writing of the Length Register
Step 1: mwr 0x40400000 0x00000001
 Start Source DMA Engine
Step 2: mwr 0x40400030 0x00000001
 Start Destination DMA Engine
Step 3: mwr 0x40400018 0x00110000
 Define Source Address
Step 4: mwr 0x40400048 0x00120000
 Define Destination Address

 

PS-DDR to PL DMA Transfer begin with the writing of the Length Register
Step 5: mwr 0x40400028 0x00000400
 Write Source Length Register & Launch DMA

 

PL to PS-DDR DMA Transfer begin with the writing of the Length Register
Step 6: mwr 0x40400058 0x00000400
 Write Destination Length Register & Launch DMA

 

After the DMA Transfers, you can verify the Destination Address contents using the XSCT:

 

mrd 0x00120000 0x100
  Read 256 words starting at address 0x0012_0000

 

 

I hope you find this information useful.

 

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5 Replies
Explorer
Explorer
933 Views
Registered: ‎09-15-2011

Re: loss package between PL and PS

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2: ADC Data -> (B port)Block RAM(A port) -> Stream - > AXI DMA -> PS DDR

if we use this way, The transmission data is continuous? 

and how to ?

 

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Xilinx Employee
Xilinx Employee
1,183 Views
Registered: ‎11-30-2007

Re: loss package between PL and PS

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You can use the HP port for direct access to the PS-DDR memory.  You can use the AXI DMA to transfer the data from your PL source.

 

PS-to-PL DMA.jpg

 

If you use the AXI DMA in Simple DMA mode, the important registers are as follows.  There are 3 registers for Source and 3 registers for Destination (depending on direction of DMA).

 

AXI_DMA Registers.jpg

 

Assuming the following Memory Map:

 

DDR "Source" Address: 0x0011_0000
DDR "Destination" Address: 0x0012_0000
MM2S Source
0x4040_0000 : MM2S DMA Control Register
0x4040_0018 : MM2S Source Address (31:0) Register
0x4040_0028 : MM2S Source Length Register
S2MM Destination
0x4040_0030 : S2MM DMA Control Register
0x4040_0048 : S2MM Destination Address (31:0) Register
0x4040_0058 : S2MM Destination Length Register

 

You can use the XSCT Console (in SDK) to write to the Source Addresses (data to send to PL) and to read the Destination Addresses (to verify data from PL).  For example, use the following commands from XSCT to write specific data to the Source Address and verify the data was written as expected:

 

mwr -size w 0x00110000 {0x01234567 0x12345678 0x23456789 0x34567890 0x45678901 0x56789012 0x67890123 0x78901234 0x89012345 0x90123456 0x21436587 0xffeeddcc} 0x100
  Write 256 words starting at address 0x0011_0000 & fill with list with remaining filled by last value

 

mrd 0x00110000 0x100
  Read 256 (0x100) words starting at address 0x0011_0000

 

For DMA Transfer from PS-DDR to PL and then from PL to PS-DDR:

 

DMA Transfers begin with the writing of the Length Register
Step 1: mwr 0x40400000 0x00000001
 Start Source DMA Engine
Step 2: mwr 0x40400030 0x00000001
 Start Destination DMA Engine
Step 3: mwr 0x40400018 0x00110000
 Define Source Address
Step 4: mwr 0x40400048 0x00120000
 Define Destination Address

 

PS-DDR to PL DMA Transfer begin with the writing of the Length Register
Step 5: mwr 0x40400028 0x00000400
 Write Source Length Register & Launch DMA

 

PL to PS-DDR DMA Transfer begin with the writing of the Length Register
Step 6: mwr 0x40400058 0x00000400
 Write Destination Length Register & Launch DMA

 

After the DMA Transfers, you can verify the Destination Address contents using the XSCT:

 

mrd 0x00120000 0x100
  Read 256 words starting at address 0x0012_0000

 

 

I hope you find this information useful.

 

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Explorer
Explorer
889 Views
Registered: ‎09-15-2011

Re: loss package between PL and PS

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Hi Miker

Thank you for your reply. follow the figure 

in the PL, because we get the decimation of data from ADC device, so i write the bram A port used the wr_address, at the same time the bram B port should convert AXI stream ?

 

in the PL, we use two block ram BlockA and BlockB, the size is 1024*16bit, PL Write BlockA  and PS read BlockB, PL Write BlockB and PS read BlockA, so we call it a Package

 

 

 

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Explorer
Explorer
887 Views
Registered: ‎09-15-2011

Re: loss package between PL and PS

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in the Linux ,we want get the frame data, usually, in the project, the Frame rate is 20 fps,the Frame data is composed of 256 packages, a packages size is 1024*16bit

when BlockA RAM or BlockB RAM is full, we tell the PS, and PS can read the fullflag , if fullflag is true, PS move the Package from PL to PS DDR,

so , i want to get the data from the PL to PS DDR, and when PS read 256 packages, it's one Frame is ok, and send one Frame to PC terminal

i don't know how to get the DMA driver, and Can Linux system guarantee no loss of packets when moving data from PL to PS?

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Explorer
Explorer
784 Views
Registered: ‎09-15-2011

Re: loss package between PL and PS

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Hi Miker

Thank you for your reply!

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