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Observer mofanvshen
Observer
5,101 Views
Registered: ‎09-30-2008

operating system in fpga

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Dear!

  recently I do some research on edk, and now it is necessary to do some more about operating system embedded in fpga. Linux, a compatible operating system, is what we want to study. However, I don't know whether a third software is needed. So, some help is required about the third software, the method for gradual development.

  Desired for your letter! Meanwhile, hoping for more support from you.

                                                                                                                               yours

                                                                                                                                     maipei

 

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Explorer
Explorer
6,222 Views
Registered: ‎08-16-2008

Re: operating system in fpga

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3 Replies
Explorer
Explorer
6,223 Views
Registered: ‎08-16-2008

Re: operating system in fpga

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Observer mofanvshen
Observer
5,036 Views
Registered: ‎09-30-2008

Re: operating system in fpga

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Dear!

    I have received your reply, but I still don't understand the step of embedding Linux system into the XUP board. So a detailed introduction to that content is required.

    Hoping for your help!

                                                                                                                                                          yours

                                                                                                                                                                  maipei

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Explorer
Explorer
1,091 Views
Registered: ‎09-02-2009

Re: operating system in fpga

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Having a sequential processor implanted in the FPGA is senseless from an abstract point of view:

 

The FPGA defines millions of gates interconnect according to the HDL specification (synthesis) and the way they are defined is different from slice to slice but same from time clock cycle to next clock cycle;

 

I can have 1 billion clock cycles in a couple seconds but the FPGA will never change the way it is imprinted to have the millions of gates, so it will be 1 billion times the same structure again and again.

 

Having a sequential process that takes a couple seconds for a billion operations will always be better than the FPGA because once used it can then do something else on the same chip whereas the FPGA cannot and another FPGA imprint would be needed.

 

putting both together is rather poor for the reason that even if it can do the things differently each time and reprogrammable it will take a) a very large number of clock cycles because its sequential programming  and b) it will talk to a circuit that is imprinted forever and cannot change.

 

If you make a FPGA/CPLD circuit do Operation A in 8nS (eight nano seconds is 8 millionth of 1mS the average time of a sequential program) and the use the "embedded" sequential processor do Operation B in a reprogrammable way its all good and wonderful apart that the result of Operation A will be crippled by B so together they will no longer be fast and because A is fixed its also going to be rigid.

 

The slices have LUT that are set once for all by the synthesis tools (that makes the imprint from the synthesis) now it would be nice to be able to reprogram the LUT on the run, so one could have P-SLICES per ex that have the 2 FF where the user defines on one FF the LUT and on the other the routing to neighbors that could allow for a manual "imprint" where a user program could define imprints that can change so one would have Operation A done in 8nS and Operation B done also in 8nS and both in 16ns?

 

it would be nice but the design entry a night mare if relying on the synthesis tools that do the work, then one is lost to which LUT to change and where it is possible but would take a long time, Hence having a design entry based on schematics that one can map on slices manually would be nice and have the routing and LUT that could be "soft" in some places so the user could make the FPGA have parts "programmable" because those routing and LUT parameters would come from a memory in form of code.

 

That way I could have one FPGA do what otherwise I would need thousands or much more just to be able to compete with the regular processors.

 

I know this seems complicated but why create a bottleneck in the FPGA by fixing the LUT parameters once for all when the normal processors also have a bottleneck so the end effect is no real gain in performance when the industry is really in need of magnitudes faster arrays?

 

Is there any works or papers on that subject or literature or names of some that done work on it

 

Here I done an attempt how to inject LUT I only managed an AND gate and ADD operation but I'm adding it here for those wondering about getting an OS on FPGA in fact the Operating System is what runs programs so we have here for one Operation A with severall sub-codes on FPGA that on the next clock cycle can be re-configured to Operations B, so the good news is that is possible now~

 

Here the link press the licence that opens the page (I want to protect my work but still show it!) where one can scroll to the right and see how the "soft ADD" is done on 4 bits here

http://www.xlyns.com/Muxcodes-Programing.html

 

thanks everyone for the amazing help
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