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Adventurer
Adventurer
7,233 Views
Registered: ‎01-13-2015

s_axis_tdata width of AXI4-Stream switch

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Hi all,

 

I'm using an AXI4-Stream Swithc core. and there are two slave interfaces and one master interface.

I set TDATA width to 1 byte. and master interface's tdata width is 8-bit. But each slave interface's tdata width is 16-bit.

When I set them to 2 byte, slave's tdata is 32-bit and master is 16-bit. This does not make a sense.

I think both slave and master's tdata width should be same.

 

Why slaves' tdata width are twice than master's one?

AXI4_Stream_Switch.jpg

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Community Manager
Community Manager
13,736 Views
Registered: ‎06-14-2012

Re: s_axis_tdata width of AXI4-Stream switch

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This is expected when using the crossbar/switch cores. All the signals for each channel are concatenated together. The customer should use the AXI Stream Interconnect instead of the Switch to get the normal situation where the channels are all broken apart. The Interconnect also has all the additional features (resizer, fifos, register slices, etc) that the Switch lacks.

 

slave _tdata = master_tdata * number of slaves and master_tdata = slave_tdata * number of masters

It is in simple numerical order. In other words: tdata[15:0] -> slave0, tdata[31:16] -> slave1, ... and so on

If I select 2 slaves and 1 master with 1 byte as tdata width, IP block diagram shows s0_axis_tdata(15:0) , s1_axis_tdata(15:0) and master M00_axis_tdata(7:0)
But the wrapper has only s_axis_tdata(15:0)

Check the wrapper also.

 

Regards

Sikta

1 Reply
Community Manager
Community Manager
13,737 Views
Registered: ‎06-14-2012

Re: s_axis_tdata width of AXI4-Stream switch

Jump to solution

This is expected when using the crossbar/switch cores. All the signals for each channel are concatenated together. The customer should use the AXI Stream Interconnect instead of the Switch to get the normal situation where the channels are all broken apart. The Interconnect also has all the additional features (resizer, fifos, register slices, etc) that the Switch lacks.

 

slave _tdata = master_tdata * number of slaves and master_tdata = slave_tdata * number of masters

It is in simple numerical order. In other words: tdata[15:0] -> slave0, tdata[31:16] -> slave1, ... and so on

If I select 2 slaves and 1 master with 1 byte as tdata width, IP block diagram shows s0_axis_tdata(15:0) , s1_axis_tdata(15:0) and master M00_axis_tdata(7:0)
But the wrapper has only s_axis_tdata(15:0)

Check the wrapper also.

 

Regards

Sikta