UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Scholar embedded
Scholar
6,189 Views
Registered: ‎06-09-2011

uBlaze doesn't work in ISE 14.7

Hi,

I have designed a uBlaze system and could simulate it with ModelSim SE in EDK14.7. All signals like GPio and UART were behaving as was written in SDK application. I used this design in my VHDL project as a sub-module and designed other parts of my design in VHDL. The problem is that after this implementation of microblaze it doesn't work at all. I have all the reset and clock signals routed and have assigned the elf file to the processor in my ISE project but it doesn't work. I see in the simulation that processor is not working. I don't see why?

It's been a long time that sience I saw this problem and unfortunately none of Xilinx professionals could answer my question!.You can see from below picture that except to input signals that are being drived from testbench uBlaze doesn't contorl any output signal. This design was working perfectly as a standalone processor.

I would appreciate any help and comment.

 


uBlaze.jpg

 

Thanks in advance,

Hossein

0 Kudos
5 Replies
Mentor hgleamon1
Mentor
6,177 Views
Registered: ‎11-14-2011

Re: uBlaze doesn't work in ISE 14.7

How are your clocks and resets connected from the top level to the instantiated embedded submodule?

 

Check your reset polarity. If you use a DCM/PLL in the embedded design check that it is reset correctly and locks to your input clock.

 

If the embedded design works standalone but doesn't work when instantiated as a submodule then at least one thing is not connected up correctly.

----------
"That which we must learn to do, we learn by doing." - Aristotle
0 Kudos
Scholar embedded
Scholar
6,170 Views
Registered: ‎06-09-2011

Re: uBlaze doesn't work in ISE 14.7

Hi,

Thank you for your answer. As I told before reset and clock pins have the same polarity which they have in stand alone mode. I made no changes in reset and clock pins in top module. Have you ever tried to use a MicroBlaze in ISE? Once I had used in ISE12.4 and it worked fine. Can this be an ISE 14.7 bug? What else causes this problem? I need to solve this issue very fast I need help I am behind my timing schedule.

 

Thanks again,

Hossein

 

 

0 Kudos
Mentor hgleamon1
Mentor
6,160 Views
Registered: ‎11-14-2011

Re: uBlaze doesn't work in ISE 14.7

Yes, I have several done uB designs, all as submodules in larger ISE designs, although I have only used them in ISE 13.4.

 

As I mentioned, you need to check your instantiation - if it works standalone but not as a submodule then something is wrong with your instantiation. My first suspicion is that you have no clock running in the embedded design. When you simulate, can you see that the clock IN THE EMBEDDED DESIGN is oscillating correctly? Are you using a DCM? Is it receiving a valid reset and locking to the incoming clock? 

 

Can you post your top level here so we can see how you are instantiating the embedded system?

----------
"That which we must learn to do, we learn by doing." - Aristotle
0 Kudos
Scholar embedded
Scholar
6,149 Views
Registered: ‎06-09-2011

Re: uBlaze doesn't work in ISE 14.7

Hi,

Thank you very much for your answer and follow up. I have just routed top vhdl signals directly - without any change - to the processor module. clock generator inside the module changes it to 100MHz. Below I have attached top VHDL, testbench and MHS file.

0 Kudos
Mentor hgleamon1
Mentor
6,137 Views
Registered: ‎11-14-2011

Re: uBlaze doesn't work in ISE 14.7

In your test bench, the differential clock signals are initialised to the same value. This may not matter as the signal assignment may override it anyway but it's not a good start.

In your MHS you define the input clock to be 50MHz but your test bench generates a 100MHz clock given its 10ns period. May be your clock generator is mixed up by this.
----------
"That which we must learn to do, we learn by doing." - Aristotle
0 Kudos