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Visitor majunwei
Visitor
7,582 Views
Registered: ‎09-01-2015

vdma fsync out not generated

Hi,

 

I am designing a simple vdma with fsync option enabled. The details are attached in picture below.

 

In the s2mm chnnel, although I can observed s2mm_fsync is there in the debugger window, but the s2mm_fsync_out never came out.

 

I'm wondering how to fix this issue?

 

Thanks,

Jeremy

vdma1.PNG
vdma2.PNG
vdma3.PNG
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3 Replies
Xilinx Employee
Xilinx Employee
7,577 Views
Registered: ‎08-02-2011

Re: vdma fsync out not generated

Hmm, can you post a screenshot of the ILA capture that you are looking at?

Are you deasserting fsync at some point?

To be sure, have you run an entire frame or two through the VDMA and still don't see it?
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Visitor majunwei
Visitor
7,572 Views
Registered: ‎09-01-2015

Re: vdma fsync out not generated

Hello,

 

The fsync signal is there and it did go high then go low. The M_AXI_S2MM interface starts to transfer data after fsync goes low. I can see in the debugger window, after multiple tlast's have passed, the fsync_out is still not high.

 

I have attached the screenshot here. The interface I'm probing is M_AXI_S2MM.

 

Also, I noticed the bresp signal is 3 which indicates decode error, but that shouldn't cause fsync_out problems.

 

Thanks,

Jeremy

vdmafsyncissue.PNG
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Xilinx Employee
Xilinx Employee
7,539 Views
Registered: ‎08-02-2011

Re: vdma fsync out not generated

Hi Jeremy,

Hmm, I'm not sure about that. It seems the response error comes on the first transaction of the frame. I'd solve that first.

Curious, what are you trying to use fsync_out for?
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