09-18-2015 08:34 AM
I am designing a simple vdma with fsync option enabled. The details are attached in picture below.
In the s2mm chnnel, although I can observed s2mm_fsync is there in the debugger window, but the s2mm_fsync_out never came out.
I'm wondering how to fix this issue?
09-18-2015 12:11 PM
09-18-2015 02:03 PM
The fsync signal is there and it did go high then go low. The M_AXI_S2MM interface starts to transfer data after fsync goes low. I can see in the debugger window, after multiple tlast's have passed, the fsync_out is still not high.
I have attached the screenshot here. The interface I'm probing is M_AXI_S2MM.
Also, I noticed the bresp signal is 3 which indicates decode error, but that shouldn't cause fsync_out problems.
09-24-2015 02:13 PM