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Adventurer
Adventurer
2,380 Views
Registered: ‎01-26-2017

zcu102 ethernet (GEM) IP block setup

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Hi,

 

I have been reading through the ZCU102 TRM about ethernet. I would like to setup my board to have 2x 1G ethernet ports (one for input, one for output, un-synchronized). I figure I will make use of the SFP+ cages provided and use one as an input, and one as an output. My IP block, largely taken from the TRM, would be something like

 

PL <-------> FIFO <-------> AXI FIFO <-------> 10/100/1000 MAC <------> PCS <---------> SFP+

 

Would this design work with the instructions given in the TRM ethernet section in terms of programming things in order, etc? Also, would any Xilinx IP need to be purchased? On other FPGAs, I've noticed that the MAC is usually Xilinx paid IP, but from what I can tell with the Zynq MPSoC MAC, it appears to be free.

 

Thanks,

Aaron

--- Estimated Development time: 2*Pi*(planned completion date) ---
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Moderator
Moderator
4,230 Views
Registered: ‎09-12-2007

Re: zcu102 ethernet (GEM) IP block setup

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See xapp1305 and xapp1306
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Moderator
Moderator
4,231 Views
Registered: ‎09-12-2007

Re: zcu102 ethernet (GEM) IP block setup

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See xapp1305 and xapp1306
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