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LukasVik
Contributor
Contributor
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Registered: ‎04-24-2020

1/10/25G Switching IP: basex_or_sgmii is not connected

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Vivado version: 2020.2
Platform: Ubuntu 18.04 64 bit
Device: Kintex UltraScale+
Xilinx IP: 1/5/10G Switching Ethernet Subsystem version 2.6

Hello,

In the 1/10/25G Switching Ethernet Subsystem, when Include Auto Negotiation (Clause-37) is enabled, the basex_or_sgmii port is not connected internally in the IP. This is indicated by the IP synthesis log:

WARNING: [Synth 8-7071] port 'basex_or_sgmii' of module 'ethernet_1_10_25g_top' is unconnected for instance 'i_ethernet_1_10_25g_top_0' [/work/build/project/project.gen/sources_1/ip/ethernet_1_10_25g/ethernet_1_10_25g_v2_6_0/ethernet_1_10_25g_wrapper.v:661]
WARNING: [Synth 8-7023] instance 'i_ethernet_1_10_25g_top_0' of module 'ethernet_1_10_25g_top' has 154 connections declared, but only 153 given [/work/build/project/project.gen/sources_1/ip/ethernet_1_10_25g/ethernet_1_10_25g_v2_6_0/ethernet_1_10_25g_wrapper.v:661]

Indeed when inspecting the generated code, ethernet_1_10_25g_top.v and ethernet_1_10_25g_wrapper.v both have an input wire basex_or_sgmii, but it is unused in ethernet_1_10_25g_wrapper.v, i.e. not connected in the instantiation of ethernet_1_10_25g_top.

The IP was created according to this TCL:

create_ip -vlnv xilinx.com:ip:ethernet_1_10_25g:2.6 -module_name ethernet_1_10_25g
set_property -dict [list \
  CONFIG.CORE "Ethernet PCS/PMA 32-bit" \
  CONFIG.DATA_PATH_INTERFACE "MII" \
  CONFIG.INCLUDE_STATISTICS_COUNTERS "0" \
  CONFIG.ADD_GT_CNTRL_STS_PORTS "1" \
  CONFIG.GT_LOCATION "0" \
  CONFIG.INCLUDE_SHARED_LOGIC "0" \
  CONFIG.INCLUDE_AXI4_INTERFACE "1" \
  CONFIG.INCLUDE_AUTO_NEG_LT_LOGIC "Include Auto Negotiation (Clause-37)"
] [get_ips ethernet_1_10_25g]

Perhaps future versions of the IP could fix this? It would be nice to be able to choose between BASE-X or SGMII.


Best regards

Lukas Vik

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1 Solution

Accepted Solutions
guozhenp
Xilinx Employee
Xilinx Employee
237 Views
Registered: ‎05-01-2013

OK. I can see the issue with your attached .xci

The issue is for the specified configurations. We'll fix it in the future.

If you generate the IP core with "Include GT subcore in core", the issue disappear.

View solution in original post

4 Replies
guozhenp
Xilinx Employee
Xilinx Employee
307 Views
Registered: ‎05-01-2013

I created an example in 2020.2. I don't see the issue.

What's the device? Please provide the IP .xci file.

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LukasVik
Contributor
Contributor
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Registered: ‎04-24-2020

Hello @guozhenp ,

I tried it again with an example design and I definitely see the issue. Perhaps we are using different device, my part name is xcku5p-ffva676-1-e. Also the .xci file is attached.

Just to be clear about the issue I'm seeing. In the example design, in the *_top.v file we see that basex_or_sgmii is an input port that is used in this module:

_top.png

 

 

 

 

 

 

However the level above, _wrapper.v, has basex_or_sgmii input port that is not used in the instantiation of _top:

_wrapper.png

 

 

 

 

 

 

This can also be seen in the synthesis log, as I noted I my first message.

Hope this helps!

 

Best regards

Lukas

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guozhenp
Xilinx Employee
Xilinx Employee
238 Views
Registered: ‎05-01-2013

OK. I can see the issue with your attached .xci

The issue is for the specified configurations. We'll fix it in the future.

If you generate the IP core with "Include GT subcore in core", the issue disappear.

View solution in original post

LukasVik
Contributor
Contributor
216 Views
Registered: ‎04-24-2020

Great, thank you! Have a nice day.

 

Best regards

Lukas

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