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Participant swarnim
Participant
353 Views
Registered: ‎05-24-2018

1000Base x PCS PMA IP on ZCU102 board

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Hi

I am working on ZCU102 board and want to design ethernet using SFPs. I went through the XAPP1305/1306 designs and was successful in replicating those and got 2 SFPs to ping data. But my objective is to design the ethernet only on PL section without involving Zynq or microblaze. So for that I used the 1000Basex PCS/PMA IP and connected the gtrefclk_in ports to the C8 pin of the ZCU102 board and the independent_clock_bufg was given via clock wizard at 50MHz. For the time being I have left the gmii ports disconnected (I tried in other approach along with TEMAC but didn't worked out).

The configuration_vector and an_adv_vector is given through constants with values "b10000" & "0x0021" respectively. The signal_detect is also connected to a constant with value 1. The reset is connected to the CPU reset button AM13.

I am expecting the resetdone on the output side of the IP to get high as soon as the bitstream is loaded and I press the CPU reset button but that doesn't happen. My bitstream generation doesn't show any errors while generation only 6-7 warnings are shown under the "methodology" tab but I dont know how to resolve them (LUT loads & bad timing practice).

 

Could anyone help as I am stuck at this I don't know why the resetdone is not going high as it should only be responsible by the clocking and reset circuitry and I could not figure out where I am going wrong. Can anyone suggest or refer some working example for ZCU102 board which I could follow to design 1G ethernet using SFP on PL side.

 

Thanks in advance.

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1 Solution

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Participant swarnim
Participant
172 Views
Registered: ‎05-24-2018

Re: 1000Base x PCS PMA IP on ZCU102 board

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Hi

Sorry for the delay. 

Yes it worked ,the resetdone pin goes high now. But it was the issue with the board clock, I had to change the clock using SCUI tool to set the boot frequency of Si570 MGT clock to 125MHz. After that and connecting the reset pin to the locked pin of clock wizard via a NOT gate made it work.

Thanks for the help anyways. Will try to get and use the data path as well with my modules now, hope that should go through.

View solution in original post

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7 Replies
Moderator
Moderator
301 Views
Registered: ‎08-25-2009

Re: 1000Base x PCS PMA IP on ZCU102 board

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Hi @swarnim ,

Are you using a 3rd party MAC or not at all?  If you do not want to involve the processor, you can use our AXI Etherent MAC core with disabling processor mode to implement it on the PL. As you already got xapp1305 and xapp1306 to work, it should be quite similar of the constraints for a non-processor mode.

The example design from Vivado can also be direclty implemented on HW to test. Please let me know if this works better.

 

"Don't forget to reply, kudo and accept as solution."
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Participant swarnim
Participant
270 Views
Registered: ‎05-24-2018

Re: 1000Base x PCS PMA IP on ZCU102 board

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Hi @nanz

Thanks for the reply. For the moment I am trying only with the PCS/PMA IP. I am attaching the screenshot of my block design. I am expecting the "resetdone" pin should go high as it indicates the transceiver is out of reset or not. But in my case this isn't going high. I am thinking that this should only concern with the clock and reset of this IP only irrespective of the MAC or GMII interface. That's correct right?

And regarding your advice on disabling processor mode in AXI Ethernet MAC, could you please elaborate a bit more design wise on how to do that and what needs to be connected on the AXI interface of MAC if not connected to the processor. Means, any separate controller code has to be written or it can be taken care by some configuration parameters only?

 

block_design_snap.png
ILA_waveform.png
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Moderator
Moderator
257 Views
Registered: ‎08-25-2009

Re: 1000Base x PCS PMA IP on ZCU102 board

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Hi @swarnim ,

Yes, the resetdone signal indicates the reset sequence of the transceiver has completed. I would suggest to run the example design simulation first and pull all the clock/reset signals to compare to your ILA captures and find out what is wrong.

Regarding non-processor mode of AXI Ethernet subsystem, the AXI interface to the processor will not be existing, ie it will the direct connection between TEMAC and PCS/PMA without the ethernet buffer. You can use configuration vectors or MDIO interface upon configuring the IPs.

 

"Don't forget to reply, kudo and accept as solution."
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Xilinx Employee
Xilinx Employee
208 Views
Registered: ‎05-01-2013

回复: 1000Base x PCS PMA IP on ZCU102 board

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Try IBERT first to confirm GT can work

Then add all GT signals in your design into ILA for debugging

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Moderator
Moderator
176 Views
Registered: ‎08-25-2009

Re: 1000Base x PCS PMA IP on ZCU102 board

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Hi @swarnim ,

Have you made any progress on this one? Do you still have questions regarding it? If your questions/issues have been resolved, could you please update this forum post and mark the appropreciate thread as "Accepted Solution" so it could benifit other forum users?

Thank you!

 

 

"Don't forget to reply, kudo and accept as solution."
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Participant swarnim
Participant
173 Views
Registered: ‎05-24-2018

Re: 1000Base x PCS PMA IP on ZCU102 board

Jump to solution

Hi

Sorry for the delay. 

Yes it worked ,the resetdone pin goes high now. But it was the issue with the board clock, I had to change the clock using SCUI tool to set the boot frequency of Si570 MGT clock to 125MHz. After that and connecting the reset pin to the locked pin of clock wizard via a NOT gate made it work.

Thanks for the help anyways. Will try to get and use the data path as well with my modules now, hope that should go through.

View solution in original post

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Moderator
Moderator
166 Views
Registered: ‎08-25-2009

Re: 1000Base x PCS PMA IP on ZCU102 board

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Hi @swarnim ,

Thanks for the updates. Can you please mark your own thread post as "Accepted Solution"? So we all know how you resolved your issue. Thank you!

 

"Don't forget to reply, kudo and accept as solution."
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