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Observer
Observer
195 Views
Registered: ‎10-06-2017

100G CMAC Issue?

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Hi there,

I have a design utilizing the 100G CMAC IP with two connected Virtex Ultrascale devices (VCU108 dev board), using Vivado 19.1, with applied patch AR72445 (https://www.xilinx.com/support/answers/72445.html).

TX/RX Flow control is set, and I can see TX pause frames correctly sent from device 1. On the RX side however, the control frames are forwarded out of the AXIS port, despite GUI config for the IP is set to disable RX control forwarding.

Furthermore, the status lines never change (stat_rx_pause_req, stat_rx_pause_valid, stat_rx_pause etc.), and the RX quanta are permanently set to seemingly random values.

Has anyone else seen this behaviour? are the TX control frames malformed somehow? How can I get those status lines to update?

 

 

RX Pause QuantaRX Pause QuantaRX StreamRX StreamGUIGUI

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Xilinx Employee
Xilinx Employee
120 Views
Registered: ‎05-01-2013

回复: 100G CMAC Issue?

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1. Have you enabled those *_gcp and *_gpp signals, by following PG203?

2. CMAC IP core example design has the Pause frame example. You can run the example design simulation to check how it works directly.

 

assign da_match_gcp = (!ctl_rx_check_mcast_gcp && !ctl_rx_check_ucast_gcp) || ((DA
== ctl_rx_pause_da_ucast) && ctl_rx_check_ucast_gcp) || ((DA == 48'h0180c2000001) &&
ctl_rx_check_mcast_gcp);
assign sa_match_gcp = !ctl_rx_check_sa_gcp || (SA == ctl_rx_pause_sa);
assign etype_match_gcp = !ctl_rx_check_etype_gcp || (ETYPE == ctl_rx_etype_gcp);
assign opcode_match_gcp = !ctl_rx_check_opcode_gcp || ((OPCODE >=
ctl_rx_opcode_min_gcp) && (OPCODE <= ctl_rx_opcode_max_gcp));
assign global_control_packet = da_match_gcp && sa_match_gcp && etype_match_gcp &&
opcode_match_gcp && ctl_rx_enable_gcp;

......

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Highlighted
Xilinx Employee
Xilinx Employee
121 Views
Registered: ‎05-01-2013

回复: 100G CMAC Issue?

Jump to solution

1. Have you enabled those *_gcp and *_gpp signals, by following PG203?

2. CMAC IP core example design has the Pause frame example. You can run the example design simulation to check how it works directly.

 

assign da_match_gcp = (!ctl_rx_check_mcast_gcp && !ctl_rx_check_ucast_gcp) || ((DA
== ctl_rx_pause_da_ucast) && ctl_rx_check_ucast_gcp) || ((DA == 48'h0180c2000001) &&
ctl_rx_check_mcast_gcp);
assign sa_match_gcp = !ctl_rx_check_sa_gcp || (SA == ctl_rx_pause_sa);
assign etype_match_gcp = !ctl_rx_check_etype_gcp || (ETYPE == ctl_rx_etype_gcp);
assign opcode_match_gcp = !ctl_rx_check_opcode_gcp || ((OPCODE >=
ctl_rx_opcode_min_gcp) && (OPCODE <= ctl_rx_opcode_max_gcp));
assign global_control_packet = da_match_gcp && sa_match_gcp && etype_match_gcp &&
opcode_match_gcp && ctl_rx_enable_gcp;

......

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