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georgios.rizeakos
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Registered: ‎10-03-2019

100G CMAC LBUS - AXI STREAM bit rate

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For the LBUS interface it seems that the 100G rate is derived from the fact that 320bits out of the 512 (4x128) are becoming available after observing the tx_mytint or rx_mtyint.(In effect 320 * 322.266MHz almost 103 Gb).

In an AXI stream bus the clock remains 322.266MHz but the bus expands to 512 bits with the tx_axis_tkeep keeping them all letting effectively.

Can you please give some pointers?

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aforencich
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Registered: ‎08-14-2013

Not sure what your question is, but yes, the AXI stream interface of 512 bits at 322 MHz is around 165 Gbps, which is significantly more than 100 Gbps.  The core will deassert tready on TX and tvalid on RX to maintain the proper rate.  The reason that the AXI stream interface rate needs to be higher than 100 Gbps has to do with frame sizing, the Ethernet interframe gap, and how AXI stream packets must always start in byte lane 0.  In this case, packets that are 65 bytes in length will waste 63 byte lanes every other clock cycle on the AXI stream interface.  The interframe gap makes up for this somewhat, IIRC if you run the numbers with a 512 bit non-segmented bus (like AXI stream) and an output gap of 24 bytes (12 byte IFG + 8 byte preamble + 4 byte FCS) you need a clock speed of around 280 MHz to get full link utilization with 65 byte frames. 

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georgios.rizeakos
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Registered: ‎10-03-2019

Could someone please respond?

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aforencich
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Registered: ‎08-14-2013

Not sure what your question is, but yes, the AXI stream interface of 512 bits at 322 MHz is around 165 Gbps, which is significantly more than 100 Gbps.  The core will deassert tready on TX and tvalid on RX to maintain the proper rate.  The reason that the AXI stream interface rate needs to be higher than 100 Gbps has to do with frame sizing, the Ethernet interframe gap, and how AXI stream packets must always start in byte lane 0.  In this case, packets that are 65 bytes in length will waste 63 byte lanes every other clock cycle on the AXI stream interface.  The interframe gap makes up for this somewhat, IIRC if you run the numbers with a 512 bit non-segmented bus (like AXI stream) and an output gap of 24 bytes (12 byte IFG + 8 byte preamble + 4 byte FCS) you need a clock speed of around 280 MHz to get full link utilization with 65 byte frames. 

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