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1,184 Views
Registered: ‎11-26-2018

100G CMAC LBUS to AXI bus for ERNIC

Hello All,

Curious about how to interface 100G CMAC LBUS to AXI for ERNIC, how is the protocol conversion achieved?

Does everyone build their own?

Thank you for your insight!

Guy

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Observer
Observer
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Registered: ‎11-09-2018

This problem also puzzles me.

I don't know the structure of AXIS from ERNIC.

So I don't konw how the protocol conversion achieved.

image.png

For example,what is the formate about this signal?

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Observer
Observer
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Registered: ‎04-16-2018

I am also considering a bridge from LBUS to AXI streaming interface. I am not using Remote Direct Memory Access (RDMA as described in ERNIC) Rather I'll be looking at some logic to map AXI streaming to/from LBUS. Curious if there is a Xilinx IP or appnote on this- or if everyone builds their own.
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Registered: ‎12-13-2018

Did anybody found a way to use this LBUS to AXI-Stream bridge without having to implement it, or upgrade to Vivado 2019.2? 

- Guilherme
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Registered: ‎11-26-2018

It appears people build their own LBUS to/from AXIS.

Starting in Vivado 2019.1, the 100G CMAC has an option for AXIS/LBUS input/output. Therefore, there is no need to deal with LBUS at all.

There is no alternative but to go forward with 2019.1+ since there are also needed upgrades to other IPs as well, including ERNIC.