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nogden
Visitor
Visitor
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Registered: ‎03-17-2021

100G CMAC and RF Data Converter

Hi,

I'm currently trying to build a block design feeding a RF data converter's output to a CMAC input in Vivado 2020.2. I'm currently reading through both user guides in order to learn and understand how each IP core works, and even tried finding a tutorial and/or Xilinx course on the CMAC (already took the RFSoC course). Unfortunately, I'm not having much luck in finding material to help aid in constructing such a design. So I wanted to ask, is it possible to connect the two cores to each other? And if so, could any resources or references on how to do so, or at least provide some guidance on how to get started doing so, be suggested? Any help would be greatly appreciated.

Regards,

nogden

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klumsde
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Moderator
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Registered: ‎04-18-2011

Hi @nogden 

We don't have any example here. Our Eval Platform Captures ADC (or loads DAC) data in either or BRAM or the DDR. Then the PS application using ethernet to ship this data in or out for display in the GUI.

I think you want to stream the data out directly but it shouldn't matter that it is RFDC, it is all just AXI stream. you may need to manage TLAST here becuase there is no TLAST on the RFDC AXISTREAM

 

Keith

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