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Observer
Observer
623 Views
Registered: ‎10-06-2017

100G CMAC as 2x50G ?

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Hi,

I have a question regarding sanity for a potential design.

Let's say we have ethernet frames coming in over 4x12.5Gb/s links (over Interlaken for example), and we wish to simply aggregate these and push the frames out over 2xSFP28 running at 25Gb/s into a switch for 50G Ethernet. We have no need for the MAC capability, simply the PHY. What IP could be used for this?

Could I simply run this through the 100G CMAC IP in a 4x25G configuration and treat two of the four segmented LBUS channels as two independent 50G connections? Or are there some physical layer aspects (handshaking/synchronization/encoding/Auto Negotiation for example) that I am not considering which would make connection to 50G Ethernet infeasible. Must I use the soft 50G IP in this case?

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Xilinx Employee
Xilinx Employee
531 Views
Registered: ‎04-16-2008

It is not possible to use the 100G CMAC US/US+ Ethernet core for a 50G Ethernet link. It will not be able to link up to a 50G Ethernet link partner.

Internal to the core a single packet is split over all 4 serial lanes. Each LBUS segment does not correlate to a single serial lane. It is not possible to only drive two LBUS lanes and have the core behave as a 50G link.

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Xilinx Employee
Xilinx Employee
587 Views
Registered: ‎04-16-2008

The US/US+ hard CMAC core only supports 100G operation. It isn't possible to only use 2 lanes of 100G Ethernet and have it behave as a 50G ethernet link without any changes to the alignment logic and data ordering. The US/US+ 100G CMAC doesn't have the ability to be reconfigured as 2, 50G Ethernet links or one 50G Ethernet link (or for that matter any other rate besides 100G). For the 100G CAUI-4 4x25G Ethernet protocol, data for one packet is sent over all 4 lanes as opposed to each lane being used for independent traffic.


We do offer soft 50G Ethernet core or soft 25G ethernet core if 2, independent 25G lanes are needed. These soft cores can be configured as MAC+PCS or PCS only.

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Observer
Observer
543 Views
Registered: ‎10-06-2017
Hi,

Thank you very much for your response.

I am still slightly unclear as to whether I can use the IP block in pure PCS mode for my purposes. The data ordering I can indeed change as I pass the data into the IP block initially...
In what way do you mean the alignment logic would need to change? Internally to the CMAC IP so this is not possible for me to write some HDL to do this?
I ask because each of the segmented LBUS channels has the "mty" signal input, which again I drive from outside the IP. Surely the alignment logic that checks or uses this is at the link level above the PCS, so if I don't use the MAC layer I don't use that logic, or regardless I can simply ignore any error signals the CMAC block raises?
Is these any sort of physical layer interaction between tx side and rx side that treats all four lanes as one so that I will not be able to interface to a 50G switch on the other side? Assuming that I am driving two of the segmented LBUS channels with Ethernet frames (that are reordered and realigned by myself to use those two lanes) and receiving them from the switch as well, without a care for performing CRC checks or anything of the like?
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Xilinx Employee
Xilinx Employee
532 Views
Registered: ‎04-16-2008

It is not possible to use the 100G CMAC US/US+ Ethernet core for a 50G Ethernet link. It will not be able to link up to a 50G Ethernet link partner.

Internal to the core a single packet is split over all 4 serial lanes. Each LBUS segment does not correlate to a single serial lane. It is not possible to only drive two LBUS lanes and have the core behave as a 50G link.

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