11-07-2019 12:08 PM
The 100G Ethernet IP comes in three type of license: Ultrascale CMAC, Soft AN/LT for US/US+ and lastly the Reed Solomon IP
1) Does the CMAC runs on Ultrascale only, can I use it on the ultrascale+ FPGA
2) The AN/LT IP version requires a paid license which is requires for KR4 and CR4 application. I believe KR4 is for a backplabe application and CR4 is for MMF application. How does the physical connection affects how the IP is used anyway.
3) My Ethernet FPGA using the MAC IP connects to a QSFP28 twinax module, which in this case represents the -CR4 application, therefore in this case do I need the paid license version?
4) If I switch out the twinax module and replace it with a MMF module. Since the MMF physical connection is defined as the -SR4 application then I should be able to use the CMAC free license, is this Correct?
11-11-2019 08:01 AM
AN/LT is required for 100GBASE-KR4 or 100GBASE-CR4 applications which is why they both require that paid license. If you switch out the QSFP module for an MMF, you should be fine to use the free license because AN/LT is not used for 100GBASE-SR4. If you use the IP with the free license, you may see a warning message in Vivado about the license; you can ignore that.
This information is available on page 8 of PG203.
12-02-2019 02:28 PM
CMAC is on both ultrascale and ultrascale plus. AFAIK, the main difference is that ultrascale plus includes a hard RS-FEC implementation while ultrascale places that in soft logic, so RS-FEC requires a separate paid license for ultrascale but is included in the free license for ultrascale plus. And you'll most likely need to enable RS-FEC, but you might be fine with AN disabled.
I have managed to establish a link between a VU3P and a Mellanox 100G NIC over a 3m QSFP28 cable with only the free CMAC license. I had to turn on RS-FEC, but the Mellanox NIC was able to bring up the link without AN. In fact, the NIC is smart enough to bring the link up in 10G (no FEC), 25G (no FEC), and 100G (with RS-FEC, doesn't work with no FEC) automatically without requiring AN. Now, it might be faster with AN enabled - it currently takes a second or so for the link to come up after resetting the FPGA or plugging in the cable.