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Observer
Observer
1,628 Views
Registered: ‎02-14-2018

100Gbps Ethernet PHY and GT transceiver wizard

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Hello!

 

I am designing the PHY layer for 100GBASE-R Ethernet application. I am working Virtex Ultrascale xcvu125-flvb2104-2-e, some QSFP+ modules and the Vivado 2017.4. I am using GT transceivers wizard in order to instantiate a core. Because I have never implement something similar before in this hardware and software, I have some questions:

 

a)

If I choose a GTY_CAUI_4 preset from the wizard, I get a core which  has two ports: gtwiz_userdata_tx_in(319:0) and gtwiz_userdata_rx_in(319:0) and has no inputs or outputs for headers. The gearbox is missing (why???).

 

For what reason are these two ports? Are these the 10 parallel lanes of a PMA? Or they are just 4 interfaces of 80 bits to serdes? I assume that I must design the PCS in my own. Right?

 

By the way, the 320 bits are not divisible with 66. So I have to convert 66 bits to 64?

 

b) If I choose a line rate of 25,87125G, four channels and a synchronous or asynchronous gearbox with CAUI mode, I get some errors about unsupported speed grade. What I am doing wrong? If I select normal mode, then the wizard does not complain.

 

Can you help me please?

 

 

 

 

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Explorer
Explorer
2,242 Views
Registered: ‎03-31-2016

Re: 100Gbps Ethernet PHY and GT transceiver wizard

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On part a) that preset is intended for use with the 100G PCS/MAC hard IP which does all the gearbox internally so it defaults to the 80bit per SERDES raw mode (no gearbox).

 

On part b) CAUI mode is intended for CAUI-10 10.3125G SERDES,  The 20 Virtual lanes of all CAUIs map well to 2:1 logic used in "CAUI Mode" and 10 Physical lanes.

 

For CAUI-4 you could do use the non "CAUI Mode" of the 64/66 gearboxes and do the 4 Physical to 20 Virtual lane mapping in your own logic.

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Explorer
Explorer
2,243 Views
Registered: ‎03-31-2016

Re: 100Gbps Ethernet PHY and GT transceiver wizard

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On part a) that preset is intended for use with the 100G PCS/MAC hard IP which does all the gearbox internally so it defaults to the 80bit per SERDES raw mode (no gearbox).

 

On part b) CAUI mode is intended for CAUI-10 10.3125G SERDES,  The 20 Virtual lanes of all CAUIs map well to 2:1 logic used in "CAUI Mode" and 10 Physical lanes.

 

For CAUI-4 you could do use the non "CAUI Mode" of the 64/66 gearboxes and do the 4 Physical to 20 Virtual lane mapping in your own logic.

View solution in original post

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Observer
Observer
1,535 Views
Registered: ‎02-14-2018

Re: 100Gbps Ethernet PHY and GT transceiver wizard

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Thanks for your reply

 

I begin to understand the GTY interface

 

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Explorer
Explorer
1,501 Views
Registered: ‎02-06-2018

Re: 100Gbps Ethernet PHY and GT transceiver wizard

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@ttzotzaros did you use 100G Ethernet IP Core subsystem?
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Observer
Observer
1,480 Views
Registered: ‎02-14-2018

Re: 100Gbps Ethernet PHY and GT transceiver wizard

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No.

 

I want the PHY only. I think that the MAC implementation can not be removed from the design

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