06-11-2019 12:13 AM
I have been trying for over two weeks just debugging a simple design which has 100 G ethernet, some bram as buffers and PCIe-DMA core. I am using VCU1525 board. My debugging shows that the initialization step of ethernet core does not work. I use axi-lite to access control registers. I could confirm that even the first command for initialization does not go through and the design gets locked up there.
During ethernet core configuration, I had set the "GT RefClk" and GT "init clock" to 156.25 MHz which appears to be default clock frequency available in VCU1525 board. PCIe user clock is 125 MHz and Ethernet core axi port for initialization is accessed through an axi-interconnect to do clock conversions (125MHz to 156.25MHz).
Ethernet reset is set up through a "preocessor system reset" IP with the orignial reset coming from PCIe. (Image attached)
I separately verified my custom logic and PCIe parts, so I am pretty sure the problem is not there. I had doubt whether the clocks or resets of the ethernet core work properly. I attached the logic analyzer to probe the "init clock" and the "sys_reset" of the ethernet core. The logic analyzer clock (for its internal use) is "gt_ref_clk_out" that comes from ethernet core.
Highly likely problem & Major question:
During logic analyzer check, the "sys_reset" was always high (even after server reset which reset the PCIe port)!
The "init clock" was also always zero!
I tested many times and the results was same. So here comes two questions:
(1) what is the proper pin numbers to be set for the free running clock (init clock) in the VCU1525? (I used 'AU19' pin following the VCU1525 user guide)
(2) Am I missing something in the core setup? (note that there is no proper example design for VCU1525 and there is no automatic way of mapping some signals like "init_clk" to the FPGA pins)
Thanks in advance
09-06-2019 01:04 PM
maybe this version 1.4 helps you: https://github.com/ralfkundel/XilinxBoardStore/tree/master/boards/Xilinx/vcu1525/1.4
I used a clk_wiz as well for the init_clk and default_300mhz_clk0 as input of the wiz. Using the gt_ref_clk_out of the IP worked fine for me too.
used board: VCU1525
09-12-2019 05:32 AM
Hi @bluesky18 ,
Can you please mark this forum post as "accepted solution" so it will benifit others?