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Explorer
Explorer
730 Views
Registered: ‎10-09-2014

100g cmac packet error in axi streaming interface in Vivado 2019.1

Hi,

I am using the CMAC with axi streaming interface, but have encoutered quite frequent packet error with rx_tuser = 1. The test I was doing is very trivial, sending a packet, wait for echo back, send again... So there is no throughput issue at all. My NIC is directly connected to the FPGA without routers, so signal integrity should be good enough. I have found that it will fail after sending hunderds of packets (I have seen 99 to 600). The image beflow is a screenshot of debug core for the rx axi stream interface in the CMAC.

I have also confirmed that the data from the LBUS has the err bit set in one of the data segments. Can anyone suggest what to check next?

Screenshot_2019-09-26_10-36-48.png

Thanks,

Jimmy

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6 Replies
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Moderator
Moderator
659 Views
Registered: ‎04-01-2018

Hi @linzhongduo 

Can you please share the ILA screenshots (or dump) capturing all the status signals of the core, that helps in understanding the issue. 

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Explorer
Explorer
643 Views
Registered: ‎10-09-2014

Hi @kgadde ,

 

I don't have it handy now, but last time I checked, only the bad frame is high for one cycle when it happended. Is this enough?

 

Thanks,

Jimmy

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Xilinx Employee
Xilinx Employee
593 Views
Registered: ‎05-01-2013

Can you try GT PMA near end loopback first? Does it have the same error?

So that CMAC RX can check the TXDATA from CMAC first in case the error is caused by the link partner

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Explorer
Explorer
575 Views
Registered: ‎10-09-2014

Hi @guozhenp  and @kgadde,

I have tried several things and hope the results are useful for you:

1) in system ibert sometimes show close eye in random channel, this is not reproducible though.

2) enabling FEC seems to fix the problem, though I am aware this is totally a workaround.

3) I tried the board in two servers, supermicro and a pcie power chassis in the same server rack. The board in chassis works fine, but not working in supermicro, with the same bitstream and cable. I set the system jitter to be 0.5ns in my design. I wonder if this is caused by different power noise level etc.

Thanks,

Jimmy

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Xilinx Employee
Xilinx Employee
542 Views
Registered: ‎05-01-2013

It looks more like an SI issue.

Maybe you can try IBERT first on the failure channel to confirm the quality first.

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Explorer
Explorer
514 Views
Registered: ‎10-09-2014

Hi @guozhenp ,

 

I did try it, as explained in my previous post. But there does not seem to be a consistent failed channel. 

 

Thanks,

Jimmy

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