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Adventurer
Adventurer
385 Views
Registered: ‎02-18-2019

10G/25G Ethernet Subsystem Latency

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In this PDF for 10G/25G Ethernet Subsystem Page 16 Table 3. The latency is given for 32 Bit MAC + PCS to be 36.8ns. Does this value includes the Transciever Latency too. 

@eschidl @nmoeller @karnanl 

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Xilinx Employee
Xilinx Employee
219 Views
Registered: ‎05-01-2013

Re: 10G/25G Ethernet Subsystem Latency

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IP core has generated GT with the specified configurations.

If you want to change GT settings, you can do it by yourself. Don't forget to do simulation to verify it after you modify the GT in IP core.

The GT in the link should bypass Gearbox, I think. Please refer to AR69011 for US+ GTY latency details.

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Xilinx Employee
Xilinx Employee
377 Views
Registered: ‎03-30-2016

Re: 10G/25G Ethernet Subsystem Latency

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Hello sankalp@96 

I believe the value provided in table 3 is the latency number for low latency version/variant of IP for BASE-R only. IP with a configuration without RX buffer/FIFO.
The value are for IP core only I dont think transceiver latency is included.

Thanks & regards
Leo

Adventurer
Adventurer
373 Views
Registered: ‎02-18-2019

Re: 10G/25G Ethernet Subsystem Latency

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@karnanl Thanks for the clarification.

So the transciever which is configured in this is Preset with 10GBASE-R. Does it have any encoding with Gearbox or is configured in RAW Mode? 

Also the buffer/fifo are the FIFO/Buffer which are used in MAC?

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Xilinx Employee
Xilinx Employee
365 Views
Registered: ‎03-30-2016

Re: 10G/25G Ethernet Subsystem Latency

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Hello sankalp@96 

>So the transciever which is configured in this is Preset with 10GBASE-R. Does it have any encoding with Gearbox or is configured in RAW Mode?

10G Ethernet transceiver should be using 64B66B Asynchronous Gearbox, not RAW mode.
Yes I believe it is based on 10GBASER preset, but please generate the IP and confirm the transceiver configuration yourself.

>Also the buffer/fifo are the FIFO/Buffer which are used in MAC?

Yes correct.

Regards
Leo

Adventurer
Adventurer
349 Views
Registered: ‎02-18-2019

Re: 10G/25G Ethernet Subsystem Latency

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Thanks @karnanl 

>10G Ethernet transceiver should be using 64B66B Asynchronous Gearbox, not RAW mode.

1. Can we use Synchronous Gearbox instead of Asynchronous Gearbox for 64B66B?

2. Also some Transceiver for Ethernet are providing the latency number so low which seems they are not using Any Gearbox.

As per AR69011 the Async Gearbox gives latency of 309-340 for 32 Bit. But as per this https://developer.xilinx.com/en/articles/low-latency-transceiver-designs-for-fintech.html they are providing latency of 26.570ns.

So I am confused. 

 

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Xilinx Employee
Xilinx Employee
220 Views
Registered: ‎05-01-2013

Re: 10G/25G Ethernet Subsystem Latency

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IP core has generated GT with the specified configurations.

If you want to change GT settings, you can do it by yourself. Don't forget to do simulation to verify it after you modify the GT in IP core.

The GT in the link should bypass Gearbox, I think. Please refer to AR69011 for US+ GTY latency details.

View solution in original post