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wzab
Mentor
Mentor
567 Views
Registered: ‎08-24-2011

10G/25G Ethernet in PCS/PMA mode - how to connect blocks with shared logic in core with blocks with shared logic in example design?

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I need to implement an entity described in VHDL with parametrized number of 10G/25G Ethernet links. So I need to implement the first one with "shared logic included in core":

wzab_0-1612021944253.png

and the next blocks with "shared logic in example design":

wzab_1-1612022004003.png

 

I have successfully used that approach with PCS/PMA core in Family 7 FPGAs. Now, with xxv_ethernet block the situation seems to be more complex.

The signals provided by the block generated with "shared logic included in core":

wzab_2-1612022120722.png

 

Do not match the signals needed by the blocks with "shared logic in example design":

wzab_3-1612022187943.png

How should I connect the signals from the "shared logic" group to the signals delivered by the first block?

 

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guozhenp
Xilinx Employee
Xilinx Employee
440 Views
Registered: ‎05-01-2013

Is this for block design? If it's normal HDL flow, you can just select all the IPs with shared logic in example design and genereate the IP core example design.

And then share the COMMON logic to the multiple IP cores in your design.

View solution in original post

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nanz
Moderator
Moderator
484 Views
Registered: ‎08-25-2009

Hi @wzab ,

Can you please update your XCI file so I can take a look? 

When I tried to generate the IP for 7 series, I see the below - left is the shared logic in Core and the right is the shared logic in example design. As you can see, you can easily connect the shared logics for both IPs. 

nanz_0-1612177488199.png

 


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wzab
Mentor
Mentor
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Registered: ‎08-24-2011

Yes, it worked for Family 7. Now I'm doing it for KCU116 with Ultrascale+, and I'm using Vivado 2020.1

I attach the XCI files.

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guozhenp
Xilinx Employee
Xilinx Employee
441 Views
Registered: ‎05-01-2013

Is this for block design? If it's normal HDL flow, you can just select all the IPs with shared logic in example design and genereate the IP core example design.

And then share the COMMON logic to the multiple IP cores in your design.

View solution in original post

wzab
Mentor
Mentor
393 Views
Registered: ‎08-24-2011

It is used in the VHDL code. Yes, probably that's the way to go. However, the whole project is Open Source. So another question is if I can place the generated code in the public github repository...

 

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guozhenp
Xilinx Employee
Xilinx Employee
364 Views
Registered: ‎05-01-2013

Yes, I think you can.

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