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Visitor emakinbo
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Registered: ‎08-09-2018

10G/25G Example Design Multi Core Duplicate Instantiations

I'm trying to instantiate the 10G/25G Ethernet IP with 2 cores on my Zynq Ultrascale+ board using the 10G/25G Ethernet Core Example Design. However, when I try to synthesize the design, I find an error where some of the modules are instantiated with the same name (like i_xxv_ethernet_timer_sync_tx) in files that I can't edit. Any suggestions as to how to change these?

 

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Visitor emakinbo
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Registered: ‎08-09-2018

Re: 10G/25G Example Design Multi Core Duplicate Instantiations

Answered my own question. The files can be edited in a different file editor and simply reloaded in the design.

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