09-06-2019 01:15 AM
Hello. I have three custom boards based on Zynq Ultrascale+ FPGA. I trying to bringup x4 10G ethernet use for it 10G/25G Ethernet Subsystem IP core. Two boards work properly, but one board does not work properly. I saw that the reference clock and system reset is ok, but GTH QPLL does not lock. In GHT wrapper only power_good signals are active, but all reset_done signals are inactive. Is this hardware problem or problem may in reset/clock subsystem? How can I debug it?
Thanks for answers.
09-07-2019 01:21 AM
check your free run clock which comes to your GT. as you said your reset done signal didn't change the problem may exist in your free run clock.
09-12-2019 12:55 AM
firstly generate example design at first and check your reset procedure. pay attention to rx_good or sm_link signals in example design set them properly.
if this test will not work properly, you should double-check your clock your GT quad selection pin assignments and your board at the end.
in checking your board be sure that your entrance clock is ok and your custom board has all of the components like your other two boards. some times lack one resistor, capacitor or bad assembly can cause a big problem, try checking with magnifier. clean your board with blowing air.
09-17-2019 08:32 PM
If IBERT works, the Hardware should be good.
Have you tried one more QPLL reset?
There're not many signals of QPLL used in the design. Maybe you can use ILA to check their status.