UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor dydykin_sv
Visitor
224 Views
Registered: ‎10-19-2018

10G/25G QPLL lock problem

Hello. I have three custom boards based on Zynq Ultrascale+ FPGA. I trying to bringup x4 10G ethernet use for it 10G/25G Ethernet Subsystem IP core. Two boards work properly, but one board does not work properly. I saw that the reference clock and system reset is ok, but GTH QPLL does not lock. In GHT wrapper only power_good signals are active, but all reset_done signals are inactive. Is this hardware problem or problem may in reset/clock subsystem? How can I debug it?

Thanks for answers.

0 Kudos
6 Replies
Adventurer
Adventurer
197 Views
Registered: ‎03-16-2019

Re: 10G/25G QPLL lock problem

check your free run clock which comes to your GT. as you said your reset done signal didn't change the problem may exist in your free run clock.

0 Kudos
Visitor dydykin_sv
Visitor
178 Views
Registered: ‎10-19-2018

Re: 10G/25G QPLL lock problem

Free run clock works properly, for free run clk I use clock from Zynq processor.

0 Kudos
Adventurer
Adventurer
173 Views
Registered: ‎03-16-2019

Re: 10G/25G QPLL lock problem

are you using example design?

0 Kudos
Visitor dydykin_sv
Visitor
156 Views
Registered: ‎10-19-2018

Re: 10G/25G QPLL lock problem

No, I work with a custom project based on example design.
It's amazing, but IBERT works on all boards.

0 Kudos
Highlighted
Adventurer
Adventurer
133 Views
Registered: ‎03-16-2019

Re: 10G/25G QPLL lock problem

firstly generate example design at first and check your reset procedure. pay attention to rx_good or sm_link signals in example design set them properly.

if this test will not work properly, you should double-check your clock your GT quad selection pin assignments and your board at the end.

in checking your board be sure that your entrance clock is ok and your custom board has all of the components like your other two boards. some times lack one resistor, capacitor or bad assembly can cause a big problem, try checking with magnifier. clean your board with blowing air. 

 

Xilinx Employee
Xilinx Employee
86 Views
Registered: ‎05-01-2013

Re: 10G/25G QPLL lock problem

If IBERT works, the Hardware should be good.

Have you tried one more QPLL reset?

There're not many signals of QPLL used in the design. Maybe you can use ILA to check their status.

0 Kudos