10G Ethernet PCS/PMA with 10GBASE-SR

[apogeedbkxilinx]

Are there any settings I need to do for the PCS/PMA to support 10GBASE-SR?  I am seeing bit errors with some SR SFP+s that don't seem to occur with LR SFP+s. Initially, I thought I needed to set the pma_pmd_type port to "111".  However, with this setting the bit errors persist.  Looking at the synthesized schematic in Vivado I see that the pma_pmd_type port only connects to the status register (makes no changes to GTH setting, etc.).

Details:

Tools: Vivado 2015.2

IP: 10G Ethernet PCS/PMA v6.0

FPGA: Kintex Ultrascale (xcku115-flvf1924-2-e)

I appreciate your help on this.

[yenigal]

Hi

The core by default uses DFE for Equalization, try changing to LPM and test it.

Generate the gtwizard design with LPM for 10GBASE_R protocol, compare the gr wrapper changes and replace in the design.

[allanherriman]

1. Have you checked that the RS0 and RS1 pins on the SFP+ have the correct value?  The correct setting will vary from module to module, so you need to check the SFP+ module datasheet to be sure.  Don't assume that values that work for your LR modules will work for your SR modules, or any other modules.  The usual symptom of incorrect RS0 and RS1 is bad BER, typically so bad that it won't give PCS sync, but sometimes only just a trickle of errors.
2. Can you narrow down the problem to either the Tx (i.e. FPGA output) or the Rx (i.e FPGA input) path?  That might help.  (Suggestion: connect to some third party equipment, e.g. an Ethernet switch, and see whether the errors show up on the switch Rx or your FPGA Rx.)  If it's a Tx problem, you can adjust TXDIFFCTRL, TXPRECURSOR and TXPOSTCURSOR.  If it's an Rx problem, you could try fiddling with the Rx equaliser, as Satish suggested.

Regards,

Allan

[apogeedbkxilinx]

Thanks for the replies.

Using the IBERT I have been able to significantly improve the BER of the SFPs.  By making adjustments to TX and RX settings, I have gotten them to the point of running for hours with zero errors in the IBERT.  However, I still get some bit errors in my packet data related test with PCS/PMA.  This might just be "the way it goes" since recent tests suggest I may be near the BER spec of the SFP, but I'm still investigating to make sure I get the best results I can.

I'll do another update to this thread when we've settled on our solution.

Regards

[allanherriman]

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apogeedbkxilinx wrote: recent tests suggest I may be near the BER spec of the SFP

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My experience has been that provided that the fibre is clean and undamaged and the optical signal level is well above the minimum (yet still below the maximum) specified for the SFP, the error rate will be much better than the BER spec of the SFP.  On my boards I measure zero errors, even over the 10km or 40km test links that I keep next to my desk (they're surprisingly small).

[apogeedbkxilinx · Accepted solution]

Thanks for the insight of all who responded.  I now have all the SFPs running error free both with IBERT and in my system level bit error test.  The final solution can in 4 parts.

1. Running the IBERT sweeps across a wide range of precursor and postcurser settings while the differential swing was set low enough to reveal the variation in eye side.  I them plotted the eye size results in a graph which made it easier to see a pattern in the results.
2. I found that disable the DFE (using low power mode equalization) gave my better results in the in my system level bit error test.
3. When testing with my system level bit error test, I found I needed wider differential swing settings than needed by the IBERT.
4. I needed to clean a connector on a couple troublesome SFPs.